James J Benjamin

US Patent:

39368645, Feb 3, 1976

Filed:

Oct 4, 1974

Appl. No.:

5/512829

Inventors:

James A. Benjamin - Boxford MA

Assignee:

Raytheon Company - Lexington MA

International Classification:

H01L 2302
H01L 2312

US Classification:

357 74

Abstract:

A microwave transistor package which will accommodate large transistor chips as well as provide sufficient space for the addition of tuning capacitors or other circuits. The lead length inside of the package is minimized. A ceramic mounting pad is brazed to an underlying copper base and a nickel aperture plate is mounted around the mounting pad. The amount of ceramic material used is much less than in prior art devices. Tuning capacitors or other devices are mounted upon the top surface nickel spacer and connected to the transistor chip. In the preferred embodiment, the entire package is hermetically sealed.

US Patent:

41077202, Aug 15, 1978

Filed:

Apr 19, 1976

Appl. No.:

5/678509

Inventors:

Robert A. Pucel - Needham MA
James A. Benjamin - Boxford MA

Assignee:

Raytheon Company - Lexington MA

International Classification:

H01L 2980
H01L 2948
H01L 2956

US Classification:

357 22

Abstract:

A high-frequency, high-power FET constructed upon a planar substrate with a repeated pattern of gate, source, and drain connections wherein any two are interconnected with metallization layers adjacent to and separated from the semiconductor substrate. The third element is interconnected with an overlay metallization layer separated from the lower two metallization layers by an insulating dielectric. The overlay layer is preferably grounded for minimum feedback capacitance.

US Patent:

40166430, Apr 12, 1977

Filed:

Apr 12, 1976

Appl. No.:

5/676033

Inventors:

Robert A. Pucel - Needham MA
James A. Benjamin - Boxford MA

Assignee:

Raytheon Company - Lexington MA

International Classification:

B01J 1700

US Classification:

29571

Abstract:

A high-frequency, high-power FET constructed upon a planar substrate with a repeated pattern of gate, source, and drain connections wherein any two are connected with metallization layers adjacent to and separated from the semiconductor substrate. The third element is interconnected with an overlay metallization layer separated from the lower two metallization layers by an insulating dielectric. The overlay layer is preferably grounded for minimum feedback capacitance.