James W Bishop

US Patent:

6415402, Jul 2, 2002

Filed:

Jan 24, 2001

Appl. No.:

09/768637

Inventors:

James W. Bishop - Newark Valley NY
George A. Fax - Round Rock TX
Robert G. Iseminger - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724, 327 18

Abstract:

A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.

US Patent:

7076724, Jul 11, 2006

Filed:

Jan 22, 2003

Appl. No.:

10/348688

Inventors:

Robert M. Cole - Endwell NY, US
James E. Bishop - Newark Valley NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H03M 13/00

US Classification:

714784, 714786

Abstract:

A system and method are provided for transferring a packet across a data link. The packet may include a stream of data symbols which is delimited by one or more framing symbols. Corruptions of the framing symbol which result in valid data symbols may be mapped to invalid symbols. If it is desired to transfer one of the valid data symbols that has been mapped to an invalid symbol, the data symbol may be replaced with an unused symbol. At the receiving end, these unused symbols are replaced with the corresponding valid data symbols. The data stream of the packet may be encoded with forward error correction information to detect and correct errors in the data stream.

US Patent:

7254697, Aug 7, 2007

Filed:

Feb 11, 2005

Appl. No.:

11/055831

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Jafar Nahidi - Round Rock TX, US
Dung Quoc Nguyen - Austin TX, US
Brian William Thompto - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712213, 712 24, 712216

Abstract:

Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a maximum number of instructions read from the IBUF per cycle. The reformatted dispatch groupings can be terminated after a single cycle, or they can remain reformatted for as many cycles as desired, depending upon need.

US Patent:

7296211, Nov 13, 2007

Filed:

Jan 22, 2003

Appl. No.:

10/348659

Inventors:

Robert M. Cole - Endwell NY, US
James E. Bishop - Newark Valley NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H03M 13/00

US Classification:

714776

Abstract:

A system and method are provided for transferring a packet across a data link. The packet may include a stream of data symbols which is delimited by one or more framing symbols. Corruptions of the framing symbol which result in valid data symbols may be mapped to invalid symbols. If it is desired to transfer one of the valid data symbols that has been mapped to an invalid symbol, the data symbol may be replaced with an unused symbol. At the receiving end, these unused symbols are replaced with the corresponding valid data symbols. The data stream of the packet may be encoded with forward error correction information to detect and correct errors in the data stream.

US Patent:

7478276, Jan 13, 2009

Filed:

Feb 10, 2005

Appl. No.:

11/054988

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Michael James Mack - Round Rock TX, US
Jafar Nahidi - Round Rock TX, US
Dung Quoc Nguyen - Austin TX, US
Jose Angel Paredes - Austin TX, US
Scott Barnett Swaney - Catskill NY, US
Brian William Thompto - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 13, 714 15, 712218

Abstract:

A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

US Patent:

7620801, Nov 17, 2009

Filed:

Feb 11, 2005

Appl. No.:

11/055848

Inventors:

James Wilson Bishop - Leander TX, US
Michael Stephen Floyd - Austin TX, US
Alexander Erik Mericas - Austin TX, US
Robert Dominick Mirabella - Round Rock TX, US
Dung Quoc Nguyen - Austin TX, US
Philip Lee Vitale - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712227

Abstract:

A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.

US Patent:

7631308, Dec 8, 2009

Filed:

Feb 11, 2005

Appl. No.:

11/055850

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Brian William Thompto - Austin TX, US
Raymond Cheung Yeung - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718102, 718103, 718104

Abstract:

A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

US Patent:

7779234, Aug 17, 2010

Filed:

Oct 23, 2007

Appl. No.:

11/877391

Inventors:

James W. Bishop - Endwell NY, US
Hung Q. Le - Austin TX, US
Dung Q. Nguyen - Austin TX, US
Wolfram Sauer - Austin TX, US
Benjamin W. Stolt - Austin TX, US
Michael T. Vaden - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712207

Abstract:

The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.

Address:

1250 Falling Br Rd, Christiansburg, VA 24073

VIN:

1FTYR10D77PA34679

Make:

FORD

Model:

RANGER

Year:

2007

Address:

4602 Vly Vw Rd, Leander, TX 78641

VIN:

JH2HE01077K605187

Make:

Chevrolet

Model:

Geo Tracker 2dr Hardtop

Year:

2007