James W Bishop

US Patent:

7254697, Aug 7, 2007

Filed:

Feb 11, 2005

Appl. No.:

11/055831

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Jafar Nahidi - Round Rock TX, US
Dung Quoc Nguyen - Austin TX, US
Brian William Thompto - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712213, 712 24, 712216

Abstract:

Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a maximum number of instructions read from the IBUF per cycle. The reformatted dispatch groupings can be terminated after a single cycle, or they can remain reformatted for as many cycles as desired, depending upon need.

US Patent:

7478276, Jan 13, 2009

Filed:

Feb 10, 2005

Appl. No.:

11/054988

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Michael James Mack - Round Rock TX, US
Jafar Nahidi - Round Rock TX, US
Dung Quoc Nguyen - Austin TX, US
Jose Angel Paredes - Austin TX, US
Scott Barnett Swaney - Catskill NY, US
Brian William Thompto - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 13, 714 15, 712218

Abstract:

A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

US Patent:

7620801, Nov 17, 2009

Filed:

Feb 11, 2005

Appl. No.:

11/055848

Inventors:

James Wilson Bishop - Leander TX, US
Michael Stephen Floyd - Austin TX, US
Alexander Erik Mericas - Austin TX, US
Robert Dominick Mirabella - Round Rock TX, US
Dung Quoc Nguyen - Austin TX, US
Philip Lee Vitale - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712227

Abstract:

A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.

US Patent:

7631308, Dec 8, 2009

Filed:

Feb 11, 2005

Appl. No.:

11/055850

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Brian William Thompto - Austin TX, US
Raymond Cheung Yeung - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718102, 718103, 718104

Abstract:

A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

US Patent:

8108655, Jan 31, 2012

Filed:

Mar 24, 2009

Appl. No.:

12/410073

Inventors:

Christopher Michael Abernathy - Austin TX, US
James Wilson Bishop - Newark Valley NY, US
Mary Douglass Brown - Austin TX, US
William Elton Burky - Austin TX, US
Robert Allen Cordes - Austin TX, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Todd Alan Venton - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/302
G06F 9/312

US Classification:

712214, 712207

Abstract:

Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

US Patent:

8418180, Apr 9, 2013

Filed:

May 30, 2008

Appl. No.:

12/129876

Inventors:

James Wilson Bishop - Leander TX, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Brian William Thompto - Austin TX, US
Raymond Cheung Yeung - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718102, 718103, 718104

Abstract:

A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

US Patent:

20060184770, Aug 17, 2006

Filed:

Feb 12, 2005

Appl. No.:

11/056878

Inventors:

James Bishop - Leander TX, US
Michael Floyd - Austin TX, US
Hung Le - Austin TX, US
Larry Leitner - Austin TX, US
Brian Thompto - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/40

US Classification:

712216000

Abstract:

In a processor, a localized workaround is activated upon the sensing of a problematic condition occurring on said processor, and then control of the deactivation of the localized workaround is superseded by a centralized controller. In a preferred embodiment, the centralized controller monitors forward progress of the processor and maintains the workaround in an active condition until a threshold level of forward progress has occurred. Optionally, the localized workaround may be re-activated while under centralized control, resetting the notion of forward progress. Using the present invention, localized workarounds perform effectively while having a minimal impact on processor performance.

US Patent:

20100257341, Oct 7, 2010

Filed:

Apr 3, 2009

Appl. No.:

12/417801

Inventors:

Mary D. Brown - Austin TX, US
James W. Bishop - Newark Valley NY, US
William E. Burky - Austin TX, US
Dung Q. Nguyen - Austin TX, US
Todd A. Venton - Autin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712216, 712214, 712 19, 712E09016, 712E09003

Abstract:

A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell. A second read port couples to the first array and comprises a second read wordline and a second read bitline. The second read wordline couples to the second latch and the first column and asserts a second available signal based on the second bit. The second read bitline couples to the first row and generates a second ready signal based on the second read wordline and the first cell.