James A Bishop

US Patent:

8108655, Jan 31, 2012

Filed:

Mar 24, 2009

Appl. No.:

12/410073

Inventors:

Christopher Michael Abernathy - Austin TX, US
James Wilson Bishop - Newark Valley NY, US
Mary Douglass Brown - Austin TX, US
William Elton Burky - Austin TX, US
Robert Allen Cordes - Austin TX, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Todd Alan Venton - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/302
G06F 9/312

US Classification:

712214, 712207

Abstract:

Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

US Patent:

20100257341, Oct 7, 2010

Filed:

Apr 3, 2009

Appl. No.:

12/417801

Inventors:

Mary D. Brown - Austin TX, US
James W. Bishop - Newark Valley NY, US
William E. Burky - Austin TX, US
Dung Q. Nguyen - Austin TX, US
Todd A. Venton - Autin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712216, 712214, 712 19, 712E09016, 712E09003

Abstract:

A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell. A second read port couples to the first array and comprises a second read wordline and a second read bitline. The second read wordline couples to the second latch and the first column and asserts a second available signal based on the second bit. The second read bitline couples to the first row and generates a second ready signal based on the second read wordline and the first cell.

US Patent:

20200301758, Sep 24, 2020

Filed:

Mar 21, 2019

Appl. No.:

16/360920

Inventors:

- Armonk NY, US
Dung Q. NGUYEN - Austin TX, US
Hung Q. LE - Austin TX, US
James W. BISHOP - Newark Valley NY, US
Brian W. THOMPTO - Austin TX, US
Susan E. EISEN - Round Rock TX, US

International Classification:

G06F 9/52
G06F 9/46
G06F 9/48

Abstract:

A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.