James B Bishop

US Patent:

7076724, Jul 11, 2006

Filed:

Jan 22, 2003

Appl. No.:

10/348688

Inventors:

Robert M. Cole - Endwell NY, US
James E. Bishop - Newark Valley NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H03M 13/00

US Classification:

714784, 714786

Abstract:

A system and method are provided for transferring a packet across a data link. The packet may include a stream of data symbols which is delimited by one or more framing symbols. Corruptions of the framing symbol which result in valid data symbols may be mapped to invalid symbols. If it is desired to transfer one of the valid data symbols that has been mapped to an invalid symbol, the data symbol may be replaced with an unused symbol. At the receiving end, these unused symbols are replaced with the corresponding valid data symbols. The data stream of the packet may be encoded with forward error correction information to detect and correct errors in the data stream.

US Patent:

7296211, Nov 13, 2007

Filed:

Jan 22, 2003

Appl. No.:

10/348659

Inventors:

Robert M. Cole - Endwell NY, US
James E. Bishop - Newark Valley NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H03M 13/00

US Classification:

714776

Abstract:

A system and method are provided for transferring a packet across a data link. The packet may include a stream of data symbols which is delimited by one or more framing symbols. Corruptions of the framing symbol which result in valid data symbols may be mapped to invalid symbols. If it is desired to transfer one of the valid data symbols that has been mapped to an invalid symbol, the data symbol may be replaced with an unused symbol. At the receiving end, these unused symbols are replaced with the corresponding valid data symbols. The data stream of the packet may be encoded with forward error correction information to detect and correct errors in the data stream.

US Patent:

7779234, Aug 17, 2010

Filed:

Oct 23, 2007

Appl. No.:

11/877391

Inventors:

James W. Bishop - Endwell NY, US
Hung Q. Le - Austin TX, US
Dung Q. Nguyen - Austin TX, US
Wolfram Sauer - Austin TX, US
Benjamin W. Stolt - Austin TX, US
Michael T. Vaden - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712207

Abstract:

The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.

US Patent:

55398758, Jul 23, 1996

Filed:

Dec 30, 1994

Appl. No.:

8/367389

Inventors:

James W. Bishop - Endicott NY
Mark L. Ciacelli - Endicott NY
Patrick W. Gallagher - Rochester MN
Stefan P. Jackowski - Endicott NY
Gregory R. Klouda - Endwell NY
Robert D. Siegl - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128
G06F 1100

US Classification:

3951821

Abstract:

In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.

US Patent:

58095250, Sep 15, 1998

Filed:

Jun 19, 1996

Appl. No.:

8/666154

Inventors:

James Wilson Bishop - Endicott NY
Charles Embrey Carmack - Rochester MN
Patrick Wayne Gallagher - Apalachin NY
Stefan Peter Jackowski - Endicott NY
Gregory Robert Klouda - Endwell NY
Robert Dwight Siegl - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711122

Abstract:

A hierarchical cache system comprises first and second pluralities of data caches and first and second respective higher level caches. The first higher level cache is coupled to the first plurality of caches and stores data of the first plurality of caches. The second higher level cache is coupled to the second plurality of caches and stores data of the second plurality of caches. First and second storage controllers access first and second respective address ranges from a main memory and the higher level cache subsystems. The first higher level cache responds to a request for data not contained in the first higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range. The second higher level cache responds to a request for data not contained in the second higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range.

US Patent:

55398952, Jul 23, 1996

Filed:

May 12, 1994

Appl. No.:

8/241910

Inventors:

James W. Bishop - Endicott NY
Charles E. Carmack - Rochester MN
Patrick W. Gallagher - Rochester MN
Stefan P. Jackowski - Endicott NY
Gregory R. Klouda - Endwell NY
Robert D. Siegl - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200
G06F 1208
G06F 1212
G06F 1300

US Classification:

395465

Abstract:

A hierarchical cache system comprises a plurality of first level cache subsystems for storing data or instructions of respective CPUs, a higher level cache subsystem containing data or instructions of the plurality of cache subsystems, and a main memory coupled to the higher level cache subsystem. A page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory, by storing the data into the main memory without copying previous contents of a store-to address of the request to the higher level cache subsystem in response to said request. Also, the page mover invalidates the previous contents in the higher level cache subsystem if already resident there when the CPU made the request. A buffering system within the page mover comprises request buffers and data segment buffers to store a segment of predetermined size of the data. When all of the request buffers have like priority and there are fewer request buffers that contain respective, outstanding requests than the number of data segment buffers, the page mover means allocates to the request buffers with outstanding requests use of the data segment buffers for which there are no outstanding requests.