James Alan Burnett

US Patent:

55411320, Jul 30, 1996

Filed:

Mar 21, 1995

Appl. No.:

8/408653

Inventors:

Robert B. Davies - Tempe AZ
Vida Ilderem - Phoenix AZ
Mark D. Griswold - Chandler AZ
Diann Dow - Chandler AZ
James E. Prendergast - Phoenix AZ
Iksung Lim - Tempe AZ
Juan Buxo - Mesa AZ
Richard D. Sivan - Austin TX
James D. Burnett - Austin TX
Frank K. Baker - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265

US Classification:

437 45

Abstract:

An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).