James C Burr

US Patent:

6348372, Feb 19, 2002

Filed:

Aug 25, 2000

Appl. No.:

09/648867

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H01L 218238

US Classification:

438223, 438224, 438282, 438370

Abstract:

To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

US Patent:

6472919, Oct 29, 2002

Filed:

Jun 1, 2001

Appl. No.:

09/872787

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03K 3356

US Classification:

327210, 327211, 327212, 327208

Abstract:

Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

US Patent:

6489224, Dec 3, 2002

Filed:

May 31, 2001

Appl. No.:

09/872419

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 21425

US Classification:

438526, 438217

Abstract:

Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors. The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. Consequently, using the method and structure of the invention, considerable versatility and design flexibility are achieved with minimum additional structural complexity.

US Patent:

6489804, Dec 3, 2002

Filed:

Jun 1, 2001

Appl. No.:

09/872786

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03K 19173

US Classification:

326 38, 326 81, 326 83

Abstract:

Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

US Patent:

6501295, Dec 31, 2002

Filed:

Jun 1, 2001

Appl. No.:

09/872840

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 2500

US Classification:

326 38, 326 41, 326113

Abstract:

Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

US Patent:

6552601, Apr 22, 2003

Filed:

May 31, 2001

Appl. No.:

09/872822

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G05F 110

US Classification:

327537, 327544

Abstract:

A method for supply gating low power electronic devices uses low threshold gating transistors. The low power devices operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be optimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

US Patent:

6583001, Jun 24, 2003

Filed:

May 18, 2001

Appl. No.:

09/860217

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 218234

US Classification:

438238, 438291, 438382

Abstract:

A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

US Patent:

6586817, Jul 1, 2003

Filed:

May 18, 2001

Appl. No.:

09/860253

Inventors:

James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 2900

US Classification:

257536, 257345, 257402, 257537, 257538, 257539

Abstract:

Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.