James R Comfort

US Patent:

20010017392, Aug 30, 2001

Filed:

Mar 22, 2001

Appl. No.:

09/814514

Inventors:

James Comfort - New City NY, US
Young Lee - Somers NY, US
Yaun Taur - Bedford NY, US
Samuel Wind - White Plains NY, US

Assignee:

International Business Machines Corporation.

International Classification:

H01L021/336
H01L029/76
H01L029/94
H01L031/062
H01L031/113
H01L031/119

US Classification:

257/410000, 257/374000, 438/269000

Abstract:

MOSFET comprising: a first semiconductor region formed in the semiconductor substrate on which the MOSFET is to be integrated, said region being defined in said semiconductor substrate by n+-type doping, a thin and short semiconductor channel being arranged perpendicular with respect to said substrate, said channel being in homo-epitaxial alignment with said first semiconductor region, a gate oxide layer formed on said semiconductor channel, a second semiconductor region formed at the opposite end of said semiconductor channel, said region being n+ doped and in homo-epitaxial alignment with said semiconductor channel, at least one gate electrode arranged between said first and second semiconductor regions such that it is separated from said semiconductor gate channel by a gate oxide layer, said first semiconductor region serving as drain and said second semiconductor region serving as source, or vice versa.

US Patent:

20110220005, Sep 15, 2011

Filed:

Mar 2, 2011

Appl. No.:

13/038865

Inventors:

James Alexander Comfort - Arlington VA, US

International Classification:

G09F 17/00

US Classification:

116173

Abstract:

Embodiments described herein comprise a mesh flag with symbols or colors upon them for the purpose of portraying them. The unique design utilizing a mesh structure enables persons within close proximity of the mesh object to see through it.The Udafan would be made up of a mesh fabric that is flexible and can have any dimensions for size, as well as any dimensions for the mesh holes. The mesh should be of a size that allows persons at close proximity (as example 0-10 ft) to view at some level of visibility past the flag to more distant objects, places, or things. The type of mesh, the fabric, and the size of the banner are all variables that can be adjusted without deviating from the purpose of the invention. The Front surface of the Udafan would portray a symbol, flag, image, or sign of whatever the user wishes portrayed.

US Patent:

57127590, Jan 27, 1998

Filed:

Dec 22, 1995

Appl. No.:

8/577165

Inventors:

Katherine Lynn Saenger - Ossining NY
James H. Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01G 4002
H01G 4008
H01G 406

US Classification:

3613214

Abstract:

A capacitor structure with a generally L-shaped non-conductor having a horizontal portion and a vertical portion, the vertical portion defining a first opening formed therein; a generally U-shaped conductor formed within the first opening; and a generally L-shaped conductor formed exterior to the generally L-shaped non-conductor.

US Patent:

59148519, Jun 22, 1999

Filed:

Dec 22, 1995

Appl. No.:

8/577178

Inventors:

Katherine Lynn Saenger - Ossining NY
James H. Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01G 406
H01G 4008
H01G 4002

US Classification:

361311

Abstract:

A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.

US Patent:

57893209, Aug 4, 1998

Filed:

Apr 23, 1996

Appl. No.:

8/636456

Inventors:

Panayotis Constantinou Andricacos - Croton-on-Hudson NY
James Hartfiel Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY
Vishnubhai Vitthalbhai Patel - Yorktown NY
Katherine Lynn Saenger - Ossining NY
Alejandro Gabriel Schrott - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438678

Abstract:

Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.

US Patent:

53087852, May 3, 1994

Filed:

Sep 1, 1993

Appl. No.:

8/115509

Inventors:

James H. Comfort - Yorktown Heights NY
David L. Harame - Mohegan Lake NY
Scott R. Stiffler - Brooklyn NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

437 67

Abstract:

The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

US Patent:

57576122, May 26, 1998

Filed:

Apr 23, 1996

Appl. No.:

8/636624

Inventors:

Raul Edmundo Acosta - White Plains NY
James Hartfiel Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY
Katherine Lynn Saenger - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01G 406

US Classification:

3613214

Abstract:

Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

US Patent:

60279664, Feb 22, 2000

Filed:

Aug 13, 1997

Appl. No.:

8/910179

Inventors:

Katherine Lynn Saenger - Ossining NY
James H. Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2170

US Classification:

438239

Abstract:

A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.