James Robert Donahue

US Patent:

48230243, Apr 18, 1989

Filed:

Jun 29, 1988

Appl. No.:

7/212833

Inventors:

Ikuo J. Sanwo - San Marcos CA
James A. Donahue - San Diego CA
Donald G. Tipon - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

H03K 500
H03K 1756
H03K 301
H03K 17687

US Classification:

307262

Abstract:

A MOS circuit for trimming a digital pulse signal by delaying the rising edge of the pulse signal for a predetermined period of time and passing the falling edge without delay. The circuit includes two MOS output transistors and a signal buffer. The signal buffer has a number of stages for delaying the pulse signal, with the number chosen to control the delay in the rising edge of the pulse signal. One of the output transistors receives the pulse signal at its drain and is enabled by the delayed pulse signal from the signal buffer to pass the pulse signal after the predetermined period of time to its source at the output of the circuit, so that the rising edge is delayed, but the falling edge is not. The other output transistor is enabled to ground the output of the circuit after the falling edge of the pulse signal. A self-booting circuit drives the gate of the one output transistor to assure that the voltage level of the trimmed signal will not be reduced by dissipation across the transistor.

US Patent:

50197282, May 28, 1991

Filed:

Sep 10, 1990

Appl. No.:

7/580017

Inventors:

Ikuo J. Sanwo - San Marcos CA
James A. Donahue - Great Falls MT

Assignee:

NCR Corporation - Dayton OH

International Classification:

H03K 19092

US Classification:

307475

Abstract:

In a high speed complementary metal-oxide-semiconductor (CMOS) inter-integrated circuit (IC) chip communication system, transmission line voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between CMOS logic levels, thus lowering bus transition and hence data transfer times. The system is versatile, and does not involve typical emitter-coupled logic (ECL) logic levels. Transceivers interfacing between IC chips and the backpanel transmit data in the reduced logic level range on a pre-charged transmission line, and receive and convert data back to CMOS levels. A limiting transistor in the transmitter portion of the transceiver limits logic low level of the transmission line. The receiver portion of the transceiver converts the voltages received to CMOS levels with the aid of a differential (sense) amplifier.