James J Ellerson

US Patent:

59201258, Jul 6, 1999

Filed:

May 9, 1997

Appl. No.:

8/853942

Inventors:

James Vernon Ellerson - Endicott NY
Joseph Funari - Vestal NY
Jack Arthur Varcoe - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257778

Abstract:

Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

US Patent:

55537693, Sep 10, 1996

Filed:

May 19, 1995

Appl. No.:

8/445382

Inventors:

James V. Ellerson - Endicott NY
Joseph Funari - Vestal NY
Jack A. Varcoe - Endwell NY

Assignee:

International Business Machine Corporation - Armonk NY

International Classification:

H01L 2150

US Classification:

2281231

Abstract:

Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

US Patent:

54149282, May 16, 1995

Filed:

Apr 2, 1993

Appl. No.:

8/042196

Inventors:

Barry A. Bonitz - Endicott NY
James V. Ellerson - Endicott NY
Kishen N. Kapur - Vestal NY
Jack M. McCreary - Apalachin NY
Irving Memis - Vestal NY
Gerald M. Vettel - Pine Island MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 334

US Classification:

29840

Abstract:

An electronic package assembly wherein a low profile package is soldered to an organic (e. g. , epoxy resin) substrate (e. g. , printed circuit board), the projecting conductive leads of the package and the solder which substantially covers these leads (and respective conductors on the substrate) having been substantially covered with encapsulant material (e. g. , polymer resin) to provide reinforcement for the solder-lead connections. The encapsulant material is dispensed about the solder and lead joints following solder reflow and solidification so as to substantially surround the solder and any portions of the leads not covered with solder. The invention has particular useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.

US Patent:

52521796, Oct 12, 1993

Filed:

Sep 28, 1992

Appl. No.:

7/951614

Inventors:

James V. Ellerson - Endicott NY
Louis J. Konrad - Endwell NY
Ronald J. Moore - Binghamton NY
Jack A. Varcoe - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B44C 122
B29C 3700

US Classification:

156655

Abstract:

A method and apparatus for selectively spray etching an epoxy encapsulated chip which is mounted to a chip carrier without damage to the chip, the chip carrier or other closely mounted chips. The apparatus includes a diaphragm which can be raised and lowered to direct the flow of etchant solution at the encapsulating material located alongside and under the chip. The encapsulating material is removed from the chip without removing the chip from the chip carrier.

US Patent:

46908331, Sep 1, 1987

Filed:

Mar 28, 1986

Appl. No.:

6/845316

Inventors:

William A. Donson - Endicott NY
James V. Ellerson - Endicott NY
Richard B. Hammer - Apalachin NY
William Lafer - Chenango Bridge NY
Keith A. Snyder - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B05D 512

US Classification:

427 96

Abstract:

A process for providing circuit lines on a substrate having a non-planar surface is provided. The process includes applying a layer of photoresist material to the substrate, selectively screen printing on non-planar areas of the substrate a screen-printable coating, photoprocessing the layer of photoresist material, and providing electrical conductive pattern on the substrate.

US Patent:

54693330, Nov 21, 1995

Filed:

Jun 1, 1994

Appl. No.:

8/252488

Inventors:

James V. Ellerson - Endicott NY
Richard J. Noreika - Endicott NY
Jack A. Varcoe - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 706
H01L 2158
H01L 2328

US Classification:

361779

Abstract:

An electronic package assembly wherein a low profile package is soldered to an organic (e. g. , epoxy resin) substrate (e. g. , printed circuit board). The assembly's projecting conductive leads are soldered. An encapsulant material (e. g. , polymer resin) is used to provide reinforcement for the solder-lead connections, the encapsulant material being dispensed only along opposing sides of the package's housing which do not include projecting leads (and which are oriented substantially normal to the stresses imposed on the package during operation wherein high temperatures are attained). This dispensing may follow solder reflow and solidification. The invention is particularly useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.

US Patent:

56691378, Sep 23, 1997

Filed:

Apr 19, 1995

Appl. No.:

8/424926

Inventors:

James Vernon Ellerson - Endicott NY
Richard Joseph Noreika - Endicott NY
Jack Arthur Varcoe - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 334

US Classification:

29840

Abstract:

An electronic package assembly wherein a low profile package is soldered to an organic (e. g. , epoxy resin) substrate (e. g. , printed circuit board). The assembly's projecting conductive leads are soldered. An encapsulant material (e. g. , polymer resin) is used to provide reinforcement for the solder-lead connections, the encapsulant material being dispensed only along opposing sides of the package's housing which do not include projecting leads (and which are oriented substantially normal to the stresses imposed on the package during operation wherein high temperatures are attained). This dispensing may follow solder reflow and solidification. The invention is particularly useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.

US Patent:

58594701, Jan 12, 1999

Filed:

Nov 12, 1992

Appl. No.:

7/974493

Inventors:

James Vernon Ellerson - Endicott NY
Joseph Funari - Vestal NY
Jack Arthur Varcoe - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257772

Abstract:

Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.