James Richard Fitzpatrick

US Patent:

20020069115, Jun 6, 2002

Filed:

Dec 1, 2000

Appl. No.:

09/726561

Inventors:

James Fitzpatrick - Newport Beach CA, US

Assignee:

Catalina Marketing International, Inc. - St. Petersburg FL

International Classification:

G06F017/60

US Classification:

705/026000

Abstract:

A method, system and computer program product for online shopping. The system on which the method and computer program product are based determines a shopping district for a customer based on customer-derived information, generates a present order list of at least one item to price, selects from a global database of retailers those selected retailers within the shopping district selling the items, and forms a selection list of the selected retailers. The list indicates the price and availability of the items on the selection list. A shopping basket including selected items and prices of the selected items is determined from the list of selected retailers. A to-be-purchased list is formed for at least a part of the shopping basket list which the customer confirms. The to-be-purchased list is used to generate purchase coupons for redemption at a confirmed retailer. Alternatively, the to-be-purchased list is direct ordered from each confirmed retailer.

US Patent:

20030088466, May 8, 2003

Filed:

Dec 7, 2000

Appl. No.:

09/730592

Inventors:

James Fitzpatrick - Newport Beach CA, US

Assignee:

Catalina Marketing International, Inc. - St. Petersburg FL

International Classification:

G06F017/60

US Classification:

705/014000

Abstract:

A novel price paid database, method, system, and computer program product in which checkout items are scanned at a plurality of stores, and a checkout computer identifies the purchased items. The checkout computer determines a price paid for each purchased item. A central computer records in a price-paid database an item identification and price-paid for each purchased items. The central computer publishes the price-paid database. The checkout computer recurrently updates the price-paid database in the central computer with the price paid for each purchased item, the customer identification (if available), the store identification, and a list price for each purchased item.

US Patent:

20220342813, Oct 27, 2022

Filed:

Apr 22, 2021

Appl. No.:

17/302064

Inventors:

- Boise ID, US
Giuseppina Puzzilli - Boise ID, US
Vamsi Pavan Rayaprolu - San Jose CA, US
Ashutosh Malshe - Fremont CA, US
James Fitzpatrick - Laguna Niguel CA, US
Shyam Sunder Raghunathan - Singapore, SG
Violante Moschiano - Avezzano, IT
Tecla Ghilardi - Trescore Balneario, IT

International Classification:

G06F 12/02
G11C 29/52
G11C 16/34

Abstract:

A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

US Patent:

20220317937, Oct 6, 2022

Filed:

Jun 23, 2022

Appl. No.:

17/848292

Inventors:

- Boise ID, US
Sivagnanam Parthasarathy - Carlsbad CA, US
James Fitzpatrick - Laguna Niguel CA, US
Patrick Robert Khayat - San Diego CA, US

International Classification:

G06F 3/06
G11C 16/26

Abstract:

A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.

US Patent:

20220300428, Sep 22, 2022

Filed:

Mar 2, 2022

Appl. No.:

17/685250

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US

International Classification:

G06F 12/0882
G06F 12/0811
G11C 11/56
G06F 12/02

Abstract:

A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

US Patent:

20220283950, Sep 8, 2022

Filed:

May 17, 2022

Appl. No.:

17/746849

Inventors:

- San Jose CA, US
Mostafa EL GAMAL - Worcester MA, US
Niranjay RAVINDRAN - Rochester MN, US
Richard David BARNDT - San Diego CA, US
Henry CHIN - Fremont CA, US
Ravi J. KUMAR - Redwood City CA, US
James FITZPATRICK - Laguna Niguel CA, US

Assignee:

Western Digital Technologies, Inc. - San Jose CA

International Classification:

G06F 12/0873
G06F 12/02
G06F 11/10
G11C 11/56
G11C 8/10

Abstract:

Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

US Patent:

20220270686, Aug 25, 2022

Filed:

May 11, 2022

Appl. No.:

17/742345

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Patrick Robert Khayat - San Diego CA, US
Sivagnanam Parthasarathy - Carlsbad CA, US

International Classification:

G11C 16/26
G11C 29/50
G11C 11/56

Abstract:

A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

US Patent:

20220246214, Aug 4, 2022

Filed:

Apr 20, 2022

Appl. No.:

17/724940

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Kishore Kumar Muchherla - Fremont CA, US

International Classification:

G11C 16/10
G06F 3/06
G11C 11/56
G11C 16/26

Abstract:

A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.