James C Goodman

US Patent:

6460124, Oct 1, 2002

Filed:

Oct 20, 2000

Appl. No.:

09/693030

Inventors:

Alain Kagi - Portland OR
James R. Goodman - Madison WI
Ravi Rajwar - Madison WI

Assignee:

Wisconsin Alumni Research Foundation - Madison WI

International Classification:

G06F 1208

US Classification:

711163, 711119, 711151

Abstract:

Critical sections of a program, providing exclusive access to shared data in a multi-processor architecture may be inferred from standard instructions and used to invoke a cache protocol that delays the response of requests of other cache and thus counter intuitively improving performance of the system. During this delay, read-only copies of data may be provided and the delay may recognize two priorities of requests, one of which is not delayed so as to improve the release of locks held by different processors.

US Patent:

6922756, Jul 26, 2005

Filed:

Dec 19, 2002

Appl. No.:

10/325069

Inventors:

Herbert H. J. Hum - Portland OR, US
James R. Goodman - Madison WI, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711145, 711141, 711142, 711143, 711144, 711146

Abstract:

Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that designates a single copy of data from which further copies can be made. A cache line in the F state is used to respond to request for a copy of the cache line. In one embodiment, the newly created copy is placed in the F state and the cache line previously in the F state is put in the Shared (S) state, or the Invalid (I) state. Thus, if the cache line is shared, one shared copy is in the F state and the remaining copies of the cache line are in the S state.

US Patent:

6954829, Oct 11, 2005

Filed:

Dec 19, 2002

Appl. No.:

10/326232

Inventors:

Robert H. Beers - Hillsboro OR, US
Herbert H. J. Hum - Portland OR, US
James R. Goodman - Madison WI, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711141, 709216, 709230, 709238

Abstract:

A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

US Patent:

7111128, Sep 19, 2006

Filed:

Dec 19, 2002

Appl. No.:

10/324711

Inventors:

Herbert H. J. Hum - Portland OR, US
James R. Goodman - Madison WI, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711141, 711147, 711148

Abstract:

The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

US Patent:

7120762, Oct 10, 2006

Filed:

Oct 19, 2001

Appl. No.:

10/037041

Inventors:

Ravi Rajwar - Madison WI, US
James R. Goodman - Madison WI, US

Assignee:

Wisconsin Alumni Research Foundation - Madison WI

International Classification:

G06F 12/14

US Classification:

711150, 711151, 711152

Abstract:

Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage.

US Patent:

7130969, Oct 31, 2006

Filed:

Dec 19, 2002

Appl. No.:

10/326234

Inventors:

Herbert H. J. Hum - Portland OR, US
James R. Goodman - Madison WI, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711141, 711146

Abstract:

Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the agent. Because the import cache and the export directory only store data that has passed through the agent, not all data transferred within a system are tracked by a single import cache or export directory.

US Patent:

7340569, Mar 4, 2008

Filed:

Feb 10, 2004

Appl. No.:

10/775448

Inventors:

James R. Goodman - Madison WI, US
Ravi Rajwar - Portland OR, US

Assignee:

Wisconsin Alumni Research Foundation - Madison WI

International Classification:

G06F 13/00

US Classification:

711151, 711152, 711150, 711158, 711141

Abstract:

Hardware resolution of data conflicts in critical sections of programs executed in shared memory computer architectures are resolved using a hardware-based ordering system and without acquisition of the lock variable.

US Patent:

7360033, Apr 15, 2008

Filed:

Jun 5, 2006

Appl. No.:

11/447384

Inventors:

Herbert H. J. Hum - Portland OR, US
James R. Goodman - Madison WI, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711141, 711147, 711148

Abstract:

The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.