James L Harper

US Patent:

6444578, Sep 3, 2002

Filed:

Feb 21, 2001

Appl. No.:

09/791024

Inventors:

Cyril Cabral, Jr. - Ossining NY
Roy Arthur Carruthers - Stormville NY
Kevin K. Chan - Staten Island NY
Guy M. Cohen - Mohegan Lake NY
Kathryn Wilder Guarini - Yorktown Heights NY
James M. Harper - Yorktown Heights NY
Christian Lavoie - Ossining NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438682, 438655, 438597, 438630

Abstract:

The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a MâSi or MâSiâGe alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

US Patent:

7384868, Jun 10, 2008

Filed:

Sep 15, 2003

Appl. No.:

10/662900

Inventors:

Cyril Cabral, Jr. - Ossining NY, US
Roy A. Carruthers - Stormville NY, US
Jia Chen - Ossining NY, US
Christophe Detavernier - Ossining NY, US
James M. Harper - Durham NH, US
Christian Lavoie - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438682, 438597, 438683

Abstract:

A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

US Patent:

8125082, Feb 28, 2012

Filed:

May 15, 2008

Appl. No.:

12/120854

Inventors:

Cyril Cabral, Jr. - Ossining NY, US
Roy A. Carruthers - Stormville NY, US
Jia Chen - Ossining NY, US
Christopher Detavernier - Ossining NY, US
James M. Harper - Durham NH, US
Christian Lavoie - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/161

US Classification:

257741, 257742, 257743, 257744

Abstract:

A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

US Patent:

20020061636, May 23, 2002

Filed:

Mar 6, 2000

Appl. No.:

09/519898

Inventors:

Cyril Cabral - Ossining NY, US
Roy Carruthers - Stormville NY, US
James Harper - Yorktown Heights NY, US
Paul Kozlowski - Hopewell Junction NY, US
Christian Lavoie - Ossining NY, US
Joseph Newbury - Tarrytown NY, US
Ronnen Roy - Ossining NY, US

International Classification:

H01L021/3205
H01L021/4763

US Classification:

438/586000

Abstract:

Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

US Patent:

20020076574, Jun 20, 2002

Filed:

Dec 18, 2000

Appl. No.:

09/740089

Inventors:

Cyril Cabral - Ossining NY, US
Roy Carruthers - Stormville NY, US
James Harper - Yorktown Heights NY, US
Chao-Kun Hu - Somers NY, US
Kim Lee - Fremont CA, US
Ismail Noyan - Yorktown Heights NY, US
Robert Rosenberg - Cortlandt Manor NY, US
Thomas Shaw - Peekskill NY, US

Assignee:

International Business Machines Corporation

International Classification:

B32B015/01

US Classification:

428/660000, 428/661000, 428/662000

Abstract:

An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu, TaTi, TaHf, TaIn, TaSn, TaZr.

US Patent:

20020151158, Oct 17, 2002

Filed:

Jun 11, 2002

Appl. No.:

10/167733

Inventors:

Cyril Cabral - Ossining NY, US
Roy Carruthers - Stormville NY, US
James Harper - Yorktown Heights NY, US
Paul Kozlowski - Hopewell Junction NY, US
Christian Lavoie - Ossining NY, US
Joseph Newbury - Tarrytown NY, US
Ronnen Roy - Ossining NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L021/28

US Classification:

438/583000

Abstract:

Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

US Patent:

20040123922, Jul 1, 2004

Filed:

Dec 31, 2002

Appl. No.:

10/334464

Inventors:

Cyril Cabral - Ossining NY, US
Roy Carruthers - Stormville NY, US
Christophe Detavernier - Ossining NY, US
James Harper - Durham NH, US
Christian Lavoie - Ossining NY, US

International Classification:

C22F001/00

US Classification:

148/527000

Abstract:

A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

US Patent:

20050176247, Aug 11, 2005

Filed:

Mar 8, 2005

Appl. No.:

11/075289

Inventors:

Cyril Cabral - Ossining NY, US
Roy Carruthers - Stormville NY, US
Christophe Detavernier - Ossining NY, US
James Harper - Durham NH, US
Christian Lavoie - Ossining NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L021/44

US Classification:

438682000

Abstract:

A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.