James A Hull

US Patent:

7155471, Dec 26, 2006

Filed:

Feb 12, 2003

Appl. No.:

10/366003

Inventors:

Peter Markstein - Woodside CA, US
Dale Morris - Steamboat Springs CO, US
James M. Hull - Saratoga CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 7/38

US Classification:

708497

Abstract:

A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discriminant. If a critical pattern is found in the discriminant, this indicates that standard rounding may give an incorrect result and further calculation is needed. The method can work for various rounding modes and types of floating point representations. The method can be implemented in a system as part of a processor instruction set or any combination of hardware, microcode, and software.

US Patent:

7680999, Mar 16, 2010

Filed:

Feb 8, 2000

Appl. No.:

09/499720

Inventors:

Dale C. Morris - Menlo Park CA, US
James M. Hull - Saratoga CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00
G06F 12/14

US Classification:

711163, 711151, 711158, 712229

Abstract:

A secure promotion mechanism promotes a current privilege level of a processor in a computer system. The current privilege level controls application instruction execution in the computer system by controlling accessibility to system resources. An operating system performs a privilege promotion instruction, which is stored in a first page of memory not writeable by an application instructions at a first privilege level. The privilege promotion instruction reads a stored previous privilege level state, compares the read previous privilege level state to the current privilege level, and if the previous privilege level state is equal to or less privileged than the current privilege level, promotes the current privilege level to a second privilege level which is higher than the first privilege level.

US Patent:

20130166378, Jun 27, 2013

Filed:

Dec 21, 2012

Appl. No.:

13/725474

Inventors:

Robin Walsh - San Francisco CA, US
James Hull - San Jose CA, US
Peter Ridge - San Jose CA, US

Assignee:

FEDERATED MEDIA PUBLISHING, LLC - San Jose CA

International Classification:

G06Q 30/02

US Classification:

705 1449

Abstract:

Methods and apparatus for optimizing content targeting with optimal topics. An exemplary method comprises determining metadata characteristics associated with topics of interest, determining an inventory of the metadata characteristics, determining performance characteristics associated with the metadata characteristics; and determining optimal topics associated with the metadata characteristics. The metadata characteristics preferably include primary metadata characteristics and ancillary metadata characteristics associated with the primary metadata characteristics, and determining the optimal topics is preferably based at least in part on the inventory of the metadata characteristics and the performance characteristics of the metadata characteristics.

US Patent:

62791265, Aug 21, 2001

Filed:

Oct 30, 1998

Appl. No.:

9/183572

Inventors:

Vishal Malik - Sunnyvale CA
Alejandro Quiroz - San Jose CA
Martin J. Whittaker - Cupertino CA
James M. Hull - Cupertino CA
Michael R. Morrell - Mountain View CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1126
G06F 1128

US Classification:

714 38

Abstract:

A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.

US Patent:

62370774, May 22, 2001

Filed:

Oct 13, 1997

Appl. No.:

8/949277

Inventors:

Harshvardhan Sharangpani - Santa Clara CA
Michael Paul Corwin - Palo Alto CA
Dale Morris - Menlo Park CA
Kent Fielden - Sunnyvale CA
Tse-Yu Yeh - Milpitas CA
Hans Mulder - San Francisco CA
James Hull - Cupertino CA

Assignee:

Idea Corporation - Cupertino CA

International Classification:

G06F 938

US Classification:

712 24

Abstract:

A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.

US Patent:

55155227, May 7, 1996

Filed:

Feb 24, 1994

Appl. No.:

8/201433

Inventors:

K. Monroe Bridges - Fremont CA
William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
James M. Hull - Cupertino CA
Michael L. Ziegler - Whitinsville MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

395468

Abstract:

A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.

US Patent:

59220651, Jul 13, 1999

Filed:

Oct 13, 1997

Appl. No.:

8/949279

Inventors:

James M. Hull - Cupertino CA
Kent Fielden - Sunnyvale CA
Hans Mulden - San Francisco CA
Harshvardhan Sharangpani - Santa Clara CA

Assignee:

Institute For The Development Of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 938

US Classification:

712 24

Abstract:

A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.