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James Te Kapcio

age ~63

from Chagrin Falls, OH

Also known as:
  • James S Kapcio
  • Jim Kapcio
Phone and address:
18094 Alden St, Orange Village, OH 44023
(440)7082622

James Kapcio Phones & Addresses

  • 18094 Alden St, Chagrin Falls, OH 44023 • (440)7082622
  • Bainbridge, OH
  • 19650 Lake Shore Blvd, Cleveland, OH 44119
  • Euclid, OH
  • Mentor, OH
  • 18094 Alden St, Chagrin Falls, OH 44023

Us Patents

  • High Speed Window And Level Function Modification For Real Time Video Processing

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  • US Patent:
    52630994, Nov 16, 1993
  • Filed:
    Nov 17, 1989
  • Appl. No.:
    7/438690
  • Inventors:
    James Kapcio - Euclid OH
    Nicholas C. Wislocki - N. Royalton OH
  • Assignee:
    Picker International, Inc. - Highland Hts. OH
  • International Classification:
    G06K 940
    G06F 1500
  • US Classification:
    382 54
  • Abstract:
    A CT scanner (10) non-invasively examines a region of interest of a patient to create an image representation that is stored in an image memory (14). Each pixel of the image representation has a relatively large number of bits of radiation intensity resolution, e. g. 14 bits or 16k levels, which is larger than the gray scale resolution of a conventional video monitor (24), e. g. 8 bits or 256 levels. A look-up table (38) digitally filters each pixel value with digital filter values to reduce the number of levels of each pixel value to the number of gray scale levels displayable by the video monitor. While the image is being displayed, the operator selectively adjusts the digital filtering to optimize the displayed image for the intended diagnostic purpose. During the vertical flyback or other non-display periods of the video monitor, a central processor (30) generates most significant bits of addresses that read digital filter longwords from a filter memory (44). A multiplexer (54) breaks each word into a plurality of filter values or bytes which are serially conveyed to the digital filter look-up table.
  • Medical Imaging System Including Use Of Dma Control For Selective Bit Mapping Of Dram And Vram Memories

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  • US Patent:
    49808281, Dec 25, 1990
  • Filed:
    Nov 25, 1988
  • Appl. No.:
    7/276144
  • Inventors:
    James Kapcio - Mentor OH
    Frederick C. Mailey - S. Euclid OH
    Joseph Y. Pai - Mayfield Hts OH
    Michael J. Petrillo - Euclid OH
  • Assignee:
    Picker International, Inc. - Highland Hts OH
  • International Classification:
    G06F 1538
  • US Classification:
    36441313
  • Abstract:
    A system is provided for a display of CT cine images stored in a hybridized memory including both dynamic random access memory (14) and video random access memory frame buffer (16). The system includes memory address space which is allocated between the VRAM and DRAM. Non-linear, chained direct memory access control (22) provides a system to write a series of 640. times. 512 pixel images directly from the frame buffer at 60 frames per second. The chaining provides a means for skipping over unused addresses at the end of a display line, thus maximizing utilization of expensive VRAM memory.
  • Direct Memory Access Control Device For Use With A Single N-Bit Bus With Mof The N-Bits Reserved For Control Signals And (N-M) Bits Reserved For Data Addresses

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  • US Patent:
    53136101, May 17, 1994
  • Filed:
    Jul 3, 1991
  • Appl. No.:
    7/725549
  • Inventors:
    David C. Oliver - Maple Heights OH
    John F. Vesel - Willowick OH
    Michael J. Petrillo - Euclid OH
    James M. Kapcio - Cleveland OH
  • Assignee:
    Picker International, Inc. - Highland Hts. OH
  • International Classification:
    G06F 1328
  • US Classification:
    395425
  • Abstract:
    A DMA control device (10) is connected with an n-bit address bus (12) by way of a bidirectional internal n-bit bus (14). The m most significant bits of signals received on the bidirectional bus (14) are reserved for carrying codes which identify or enable the DMA device to respond, to generate a load signal, to generate a count signal, and to generate an output signal. The remaining bits are reserved for address data. The load signal causes the remaining bit addresses to be loaded into counters (22) or registers (40). The count signal causes the counters (22) or a latched incrementor (44) to increment. The output signal controls three-state buffers (24, 42, 46) which cause the current address to be outputted on the bidirectional bus. In this manner, the DMA control device has only a single bus and in the embodiment of FIG. 2 replaces the counter array with a register array.

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