James M Larnerd from 1221 Mead Rd, Binghamton, NY 13901, age 66

Us Patents

Circuit Board Having Burr Free Castellated Plated Through Holes
view source
US Patent:

6483046, Nov 19, 2002
Filed:

Apr 24, 2000
Appl. No.:

09/559018
Inventors:

David E. Houser - Apalachin NY
James M. Larnerd - Binghamton NY
Jeffrey L. Lee - Vestal NY
Francis S. Poch - Apalachin NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01R 909
US Classification:

174266, 174262
Abstract:

The present invention provides a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation during conventional profiling, is removed or pre-profiled to off-set the leading edge of the plated through hole from a surface of the circuit board.

Circuitized Substrate With Split Conductive Layer, Method Of Making Same, Electrical Assembly Utilizing Same, And Information Handling System Utilizing Same
view source
US Patent:

7157646, Jan 2, 2007
Filed:

Jul 2, 2004
Appl. No.:

10/882167
Inventors:

John M. Lauffer - Waverly NY, US
James M. Larnerd - Binghamton NY, US
Voya R. Markovich - Endwell NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

H05K 1/11
US Classification:

174262, 174255, 361761, 361763, 257698
Abstract:

A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e. g. , as both power and ground elements, within a product (e. g. , electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e. g. , a mainframe computer, are also provided.

Circuitized Substrate With Filled Isolation Border, Method Of Making Same, Electrical Assembly Utilizing Same, And Information Handling System Utilizing Same
view source
US Patent:

7157647, Jan 2, 2007
Filed:

Jul 2, 2004
Appl. No.:

10/882170
Inventors:

John M. Lauffer - Waverly NY, US
James M. Larnerd - Binghamton NY, US
Voya R. Markovich - Endwell NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

H05K 1/11
US Classification:

174262, 174255, 361761, 361763, 257698
Abstract:

A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e. g. , during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e. g. , a mainframe computer, are also provided.

Method Of Making Multilayered Printed Circuit Board With Filled Conductive Holes
view source
US Patent:

7211289, May 1, 2007
Filed:

Dec 18, 2003
Appl. No.:

10/737974
Inventors:

James M. Larnerd - Binghamton NY, US
John M. Lauffer - Waverly NY, US
Voya R. Markovich - Endwell NY, US
Kostas I. Papathomas - Endicott NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

B05D 5/12
B28B 19/00
B29B 15/10
US Classification:

427 969, 427 972, 427 976, 427 977, 427 992
Abstract:

A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e. g. , with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e. g. , to serve as a pad or the like on the board's external surface.

Method Of Providing Printed Circuit Board With Conductive Holes And Board Resulting Therefrom
view source
US Patent:

7348677, Mar 25, 2008
Filed:

Apr 5, 2006
Appl. No.:

11/397713
Inventors:

James M. Larnerd - Binghamton NY, US
John M. Lauffer - Waverly NY, US
Voya R. Markovich - Endwell NY, US
Kostas I. Papathomas - Endicott NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

H01L 29/40
US Classification:

257774, 427 969
Abstract:

A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e. g. , with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e. g. , to serve as a pad or the like on the board's external surface.

Method Of Making Circuitized Substrate With Split Conductive Layer And Information Handling System Utilizing Same
view source
US Patent:

7377033, May 27, 2008
Filed:

Dec 20, 2006
Appl. No.:

11/641810
Inventors:

John M. Lauffer - Waverly NY, US
James M. Larnerd - Binghamton NY, US
Voya R. Markovich - Endwell NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

H01K 3/10
US Classification:

29852, 29830, 29850, 29858
Abstract:

A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e. g. , as both power and ground elements, within a product (e. g. , electrical assembly) which includes the substrate as part thereof. An information handling system, e. g. , a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.

Information Handling System Utilizing Circuitized Substrate With Split Conductive Layer
view source
US Patent:

7491896, Feb 17, 2009
Filed:

Jan 18, 2008
Appl. No.:

12/010004
Inventors:

John M. Lauffer - Waverly NY, US
James M. Larnerd - Binghamton NY, US
Voya R. Markovich - Endwell NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

H05K 1/11
US Classification:

174262, 174255, 174263, 174264, 174265, 174266, 361761, 361763, 257698
Abstract:

An information handling system, e. g. , a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e. g. , as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.

Method Of Making Circuitized Substrate With Filled Isolation Border
view source
US Patent:

7814649, Oct 19, 2010
Filed:

Jul 10, 2006
Appl. No.:

11/482945
Inventors:

John M. Lauffer - Waverly NY, US
James M. Larnerd - Binghamton NY, US
Voya R. Markovich - Endwell NY, US
Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY
International Classification:

H05K 3/02
H05K 3/10
US Classification:

29846, 29829, 29830, 174255, 174256
Abstract:

A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e. g. , during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.