James E Littleton

US Patent:

53554850, Oct 11, 1994

Filed:

Mar 3, 1993

Appl. No.:

8/025901

Inventors:

Michael A. Denio - Sugar Land TX
James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1300

US Classification:

395650

Abstract:

A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. The function may have an argument that requires a large amount of argument data. Each extended function is associated with a special entry point command, which is in turn, associated with a communications routine that handles the transfer of the large argument data from the first processor to the second processor in bursts.

US Patent:

55465536, Aug 13, 1996

Filed:

Dec 15, 1994

Appl. No.:

8/359324

Inventors:

Iain C. Robertson - Cople, GB2
Jeffrey L. Nye - Houston TX
Michael D. Asal - Sugar Land TX
Graham B. Short - Bedford, GB2
Richard D. Simpson - Carlton, GB2
James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1200

US Classification:

395405

Abstract:

A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

US Patent:

51095041, Apr 28, 1992

Filed:

Dec 29, 1989

Appl. No.:

7/458939

Inventors:

James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 900

US Classification:

395500

Abstract:

An adapter for modifying graphics software programs at load time. The invention is a process, which may be part of a hardware or firmware configuration used with a computer system, and which scans the program for selected instructions representing routines to be replaced with a substitute routine. If such an instruction is encountered, the instruction is replaced with an interrupt trap. The substitute graphics routine is located at an address stored at the interrupt trap location.

US Patent:

52476782, Sep 21, 1993

Filed:

Oct 12, 1989

Appl. No.:

7/420491

Inventors:

James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 944
G06F 940
G06F 1516

US Classification:

395700

Abstract:

A method used in a multiprocessor computer system for linking extended functions, which are to be called from an application program running on a host processor and executed by a subprocessor, to primitive functions to be executed by the subprocessor. The extended functions may be created independently of the primitive functions, collected in a special partially linked load module, stored, and dynamically linked to other code at run time of the application program.

US Patent:

61548243, Nov 28, 2000

Filed:

Jun 7, 1995

Appl. No.:

8/474866

Inventors:

Iain C. Robertson - Cople, GB
Jeffrey L. Nye - Houston TX
Michael D. Asal - Sugar Land TX
Graham B. Short - Bedford, GB
Richard D. Simpson - Bedford, GB
James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1200

US Classification:

711202

Abstract:

A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

US Patent:

51612127, Nov 3, 1992

Filed:

Oct 12, 1989

Appl. No.:

7/420206

Inventors:

James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1520

US Classification:

395118

Abstract:

A method for handling a cursor during a graphics drawing routine that eliminates the need to insert cursor handling code into graphics function definitions. The method coordinates the placement of the cursor in screen memory with the reading out of the scan lines containing the cursor. During this time, the cursor background is saved in offscreen memory. The cursor is protected by a cursor violation region, and drawing may continue while the cursor is in screen memory so long as the cursor violation region is not infringed, in which case drawing ceases until the cursor is read out of memory. The method prevents the cursor from flickering and maximizes the availability of screen memory to the drawing routine.

US Patent:

56384246, Jun 10, 1997

Filed:

Feb 29, 1996

Appl. No.:

8/610079

Inventors:

Michael A. Denio - Sugarland TX
James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04M 164

US Classification:

379 67

Abstract:

Apparatus and a method are disclosed for establishing communication between a sending system and a receiving system. Upon initiation of the communication, the sending system sequentially monitors the receiving system for a response from one of a human interface, a non-cooperating system or a cooperating system. If a response from a human interface within the receiving system is received by the sending system, the sending system transmits a message to a human. If a response is not received from a human interface but is received from a non-cooperating system within the receiving system, the sending system transmits a message to an answering machine. If a response is not received from a human interface or a non-cooperating system, but is received from a cooperating system within the receiving system, information is exchanged between the sending system and the cooperating system in an attempt to establish communication.

US Patent:

61890774, Feb 13, 2001

Filed:

Jun 7, 1995

Appl. No.:

8/476786

Inventors:

Iain C. Robertson - Bedfordshire, GB
Jeffrey L. Nye - Houston TX
Michael D. Asal - Sugar Land TX
Graham B. Short - Bedford, GB
Richard D. Simpson - Bedford, GB
James G. Littleton - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1200

US Classification:

711149

Abstract:

An access circuit for data swapping between two computers and a computer system including the access circuit. Each computer including an address bus for supplying addresses and a data bus for transferring data. The access circuit includes a register file and two address decoder circuits. The register file has a plurality of storage locations for storing data. The register file has dual data ports capable of simultaneous data transfer via the first data port with a first data storage location and via the second data port with a second, different storage location. Each address decoder is connected to the address bus of a corresponding computer and the register file. The address decoders translate an address received on the address bus to a storage location of the register file. Two handshakes circuits are connected to respective address decoders and digital computers. The first and second address decoders are connected to each other.