James R Macdonald

US Patent:

6385632, May 7, 2002

Filed:

Jun 18, 1999

Appl. No.:

09/336393

Inventors:

Gwangwoo Choe - Austin TX
James R. MacDonald - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 102

US Classification:

708270, 708276, 712 7

Abstract:

A system and method for evaluating one or more functions using a succession of CORDIC stages/iterations followed by a residual rotation. The succession of CORDIC stages are preferably partitioned into (a) a Z path which operates on an input angle and generates an output angle, and (b) an X/Y path which operates on an input point and generates an output point. The residual rotation rotates the output point by the output angle to generate a resultant point using a small angle approximation for sine and an accurate evaluation for sine of the output angle. The number of CORDIC stages in the succession is chosen so that the error in the coordinates of the resultant point induced by the approximation of sine is smaller than a desired amount. In particular, the number of CORDIC stages in the succession is chosen to be greater than or equal to (N+1)/3 in order to guarantee N bits of precision in coordinates of the resultant point. The Z path has a propagation time which is smaller than the X/Y path.

US Patent:

6434582, Aug 13, 2002

Filed:

Jun 18, 1999

Appl. No.:

09/336394

Inventors:

Gwangwoo Choe - Austin TX
James R. MacDonald - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 102

US Classification:

708276, 708440

Abstract:

A system and method for computing the cosine of an input value. The system comprises a logical processing unit and an addition unit. The logical processing unit comprises an input bus with a plurality of input lines for receiving an input angle value. The logical processing unit includes a first plurality of gates, preferably AND gates, coupled to the input bus. Each gate of the first plurality of gates couples to two or more of the input lines. The logical processing unit generates N output operands on N corresponding output buses. At least one of the output buses includes (a) at least one output line coupled to an output of one of the first plurality of gates, and (b) at least one output line coupled to one of the input lines of the input bus. The number N of output buses is greater than or equal to two. The addition unit couples to the N output buses of the logical processing unit, and is configured to perform an addition of the N binary operands provided on the N output buses.

US Patent:

6484193, Nov 19, 2002

Filed:

Jul 30, 1999

Appl. No.:

09/365160

Inventors:

Gwangwoo Johnny Choe - Austin TX
James R. MacDonald - Buda TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 752

US Classification:

708625, 708629

Abstract:

A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit.

US Patent:

6550059, Apr 15, 2003

Filed:

Oct 4, 1999

Appl. No.:

09/412030

Inventors:

Gwangwoo “Johnny” Choe - Austin TX
James R. MacDonald - Buda TX
Paul B. Mann - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 945

US Classification:

717159, 717149, 717154

Abstract:

A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e. g. , non-loop) source instructions. Memory locations are assigned to the corresponding operands based on the operations which are selected for parallel execution, so that parallel operations operate on data which are adjacent in memory. The memory locations are assigned in a way which minimizes realignment of the data (i. e. , swapping positions of two operands. ) Another embodiment comprises a software program (e. g. , a vectorizing compiler) which examines a block of program code, analyzes the operators within the code and generates vectorized code in accordance with the foregoing method.

US Patent:

6825786, Nov 30, 2004

Filed:

May 6, 2003

Appl. No.:

10/430863

Inventors:

James R. MacDonald - Buda TX
Drew J. Dutton - Austin TX
Stephen Cox - Lakeway TX

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

H03M 166

US Classification:

341144, 341139

Abstract:

A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e. g. , frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.

US Patent:

7222252, May 22, 2007

Filed:

Feb 13, 2003

Appl. No.:

10/366189

Inventors:

Drew J. Dutton - Austin TX, US
James R. MacDonald - Buda TX, US
Stephen Cox - Lakeway TX, US

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

G06F 1/00
G06F 1/32

US Classification:

713323, 713300, 713320, 713324

Abstract:

A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

US Patent:

7310498, Dec 18, 2007

Filed:

Apr 9, 2003

Appl. No.:

10/410088

Inventors:

Trenton B. Henry - Austin TX, US
Klaas Wortel - Phoenix AZ, US
Guy A. Stewart - Leander TX, US
Henry Wurzburg - Austin TX, US
James R. MacDonald - Buda TX, US

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

H04B 7/00

US Classification:

455 412, 455 411, 455509, 455516

Abstract:

A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from an RF peripheral device. If the RF channel becomes busy and/or jammed, the RF peripheral device may tune into a predetermined channel while the computer scans for another channel to use. Once the computer finds a better channel, the computer may go to the predetermined channel and broadcast the new channel location to the RF peripheral device. In addition, if an RF signal arrives incomplete or corrupt, the computer may transmit a negative acknowledgement to the RF peripheral device, which may retransmit the previous RF signal.

US Patent:

7685450, Mar 23, 2010

Filed:

Feb 13, 2007

Appl. No.:

11/674450

Inventors:

Drew J. Dutton - Austin TX, US
James R. MacDonald - Buda TX, US
Stephen Cox - Lakeway TX, US

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

G06F 1/00

US Classification:

713324, 713320, 713300, 713323

Abstract:

A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Address:

7802 Pickford Knl Ct, Houston, TX 77041

VIN:

5TDZA3EH5AS005987

Make:

TOYOTA

Model:

HIGHLANDER

Year:

2010