James F Mccall

US Patent:

6747483, Jun 8, 2004

Filed:

May 1, 2002

Appl. No.:

10/136920

Inventors:

Hing Y To - Folsom CA
James A McCall - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 190175

US Classification:

326 86, 326 80, 326 83

Abstract:

A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.

US Patent:

7010637, Mar 7, 2006

Filed:

May 2, 2002

Appl. No.:

10/138540

Inventors:

Hing Y To - Folsom CA, US
James A McCall - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00
H03K 19/0948

US Classification:

710305, 326 83, 326 86

Abstract:

A system for interfacing over a multi-drop bus comprising a single-ended control interface coupled with a first power supply, and a common supply and a plurality of single-ended memory interfaces coupled with a second power supply, the common supply and coupled directly to the control interface. The control interface is configured to drive a control output signal and the memory interface is configured to drive a memory output signal. The output signals are driven to the common supply to transfer a logic low.

US Patent:

20190213148, Jul 11, 2019

Filed:

Dec 3, 2018

Appl. No.:

16/208224

Inventors:

- Santa Clara CA, US
Christopher E. COX - Placerville CA, US
Kuljit S. BAINS - Olympia WA, US
George VERGIS - Portland OR, US
James A. McCALL - Portland OR, US
Chong J. ZHAO - West Linn OR, US
Suneeta SAH - Portland OR, US
Pete D. VOGT - Boulder CO, US
John R. GOLES - Folsom CA, US

International Classification:

G06F 13/16
G06F 13/40
G11C 14/00
G11C 11/4096

Abstract:

Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

US Patent:

20180102162, Apr 12, 2018

Filed:

Oct 9, 2017

Appl. No.:

15/727850

Inventors:

- Santa Clara CA, US
Aaron Martin - El Dorado Hills CA, US
James A. McCall - Portland OR, US

International Classification:

G11C 11/4076
H04L 7/033
G11C 7/22
H03K 5/14
G06F 1/10
G11C 7/10
H03K 5/00

Abstract:

Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

US Patent:

20170243627, Aug 24, 2017

Filed:

Feb 18, 2016

Appl. No.:

15/047427

Inventors:

- Santa Clara CA, US
Aaron Martin - El Dorado Hills CA, US
James A. McCall - Portland OR, US

International Classification:

G11C 11/4076
H03K 5/14

Abstract:

Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.