James M Nolan

US Patent:

8291094, Oct 16, 2012

Filed:

Mar 20, 2006

Appl. No.:

11/384779

Inventors:

Raju C. Bopardikar - Carlisle MA, US
Jacob Y. Bast - Framingham MA, US
Gary A. Cardone - Groton MA, US
David E. Kaufman - Sharon MA, US
Stuart P. MacEachern - Hopkinton MA, US
Bruce D. McLeod - Sudbury MA, US
James M. Nolan - Holliston MA, US
Zdenek Radouch - Newton MA, US
Jack J. Stiffler - Marion MA, US
James A. Wentworth - Shrewsbury MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/16

US Classification:

709229, 709231, 709238

Abstract:

A data system architecture is described that allows multiple processing and storage resources to be connected to multiple clients so as 1) to distribute the clients' workload efficiently across the available resources; and 2) to enable scaleable expansion, both in terms of the number of clients and in the number of resources. The major features of the architecture are separate, modular, client and resource elements that can be added independently, a high-performance cross-bar data switch interconnecting these various elements, separate serial communication paths for controlling the cross-bar switch settings, separate communication paths for passing control information among the various elements and a resource utilization methodology that enables clients to distribute processing or storage tasks across all available resources, thereby eliminating “hot spots” resulting from uneven utilization of those resources.

US Patent:

20060161642, Jul 20, 2006

Filed:

Mar 20, 2006

Appl. No.:

11/384756

Inventors:

Raju Bopardikar - Carlisle MA, US
Jacob Bast - Framingham MA, US
Gary Cardone - Groton MA, US
David Kaufman - Sharon MA, US
Stuart MacEachern - Hopkinton MA, US
Bruce McLeod - Sudbury MA, US
James Nolan - Holliston MA, US
Zdenek Radouch - Newton MA, US
Jack Stiffler - Marion MA, US
James Wentworth - Shrewsbury MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/16

US Classification:

709219000

Abstract:

A data system architecture is described that allows multiple processing and storage resources to be connected to multiple clients so as 1) to distribute the clients' workload efficiently across the available resources; and 2) to enable scaleable expansion, both in terms of the number of clients and in the number of resources. The major features of the architecture are separate, modular, client and resource elements that can be added independently, a high-performance cross-bar data switch interconnecting these various elements, separate serial communication paths for controlling the cross-bar switch settings, separate communication paths for passing control information among the various elements and a resource utilization methodology that enables clients to distribute processing or storage tasks across all available resources, thereby eliminating “hot spots” resulting from uneven utilization of those resources.

US Patent:

48191540, Apr 4, 1989

Filed:

Dec 4, 1986

Appl. No.:

6/937978

Inventors:

Jack J. Stiffler - Concord MA
Michael J. Budwey - Holliston MA
James M. Nolan - Holliston MA

Assignee:

Sequoia Systems, Inc. - Marlborough MA

International Classification:

G06Z 1116

US Classification:

364200

Abstract:

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks.

US Patent:

45410941, Sep 10, 1985

Filed:

Mar 21, 1983

Appl. No.:

6/477536

Inventors:

Jack J. Stiffler - Concord MA
Michael J. Budwey - Holliston MA
James M. Nolan - Holliston MA

Assignee:

Sequoia Systems, Inc. - Marlboro MA

International Classification:

G06F 1116

US Classification:

371 68

Abstract:

Circuitry for a fault-tolerant computer is disclosed which circuitry is constructed in two identical halves. Each half, by itself, is not a functionally-complete circuit, however, the two identical halves can be connected together to provide a functionally-complete circuit. Each of the two circuit halves is considerably less complex than a functionally-complete circuit yet, when connected together, the two halves provide fault detection capabilities equivalent to a computer system in which the outputs of two functionally-complete, redundant circuits are compared to detect faults. In particular, each inventive circuit half contains a complete data processing and control unit but only one half of the memory which is necessary for a functionally-complete unit. The processing units on each circuit half operate simultaneously on identical data and the same address information is provided to the memories on each circuit half. To provide error detection, address information and data sent from each control unit to its associated memory is compared between circuit halves.

US Patent:

46548190, Mar 31, 1987

Filed:

Jun 28, 1985

Appl. No.:

6/750652

Inventors:

Jack J. Stiffler - Concord MA
Michael J. Budwey - Holliston MA
James M. Nolan - Holliston MA

Assignee:

Sequoia Systems, Inc. - Marlborough MA

International Classification:

G06F 1116

US Classification:

364900

Abstract:

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks.

US Patent:

44842732, Nov 20, 1984

Filed:

Sep 3, 1982

Appl. No.:

6/414961

Inventors:

Jack J. Stiffler - Concord MA
Richard A. Karp - Bedford MA
James M. Nolan - Holliston MA
Michael J. Budwey - Holliston MA
David A. Wallace - Chelmsford MA

Assignee:

Sequoia Systems, Inc. - Marlborough MA

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.

US Patent:

46086315, Aug 26, 1986

Filed:

Nov 19, 1984

Appl. No.:

6/672799

Inventors:

Jack J. Stiffler - Concord MA
Richard A. Karp - Bedford MA
James M. Nolan - Holliston MA
Michael J. Budwey - Holliston MA
David A. Wallace - Chelmsford MA

Assignee:

Sequoia Systems, Inc. - Marlborough MA

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.

US Patent:

20150140104, May 21, 2015

Filed:

Sep 15, 2014

Appl. No.:

14/485875

Inventors:

- Sodertalje, SE
James Martin NOLAN III - Cambridge MA, US
Eyoung SHIN - Cambridge MA, US
Young-Ho SONG - Cambridge MA, US
Greg TROIANO - Cambridge MA, US
Hong WANG - Cambridge MA, US

Assignee:

ASTRAZENECA AB - Sodertalje

International Classification:

C07D 403/12
A61K 31/675
A61K 9/16
A61K 45/06

US Classification:

424489, 544284, 51426623

Abstract:

Described herein are polymeric nanoparticles that include a therapeutic agent which is 2-(3-((7-(3-(ethyl(2-hydroxyethyl)amino)propoxy)quinazolin-4-yl)amino)-1H-pyrazol-5-yl)-N-(3-fluorophenyl)acetamide (also known as AZD1152 hqpa) or a pharmaceutically acceptable salt thereof, and methods of making and using such therapeutic nanoparticles.