James M Preston

US Patent:

57152489, Feb 3, 1998

Filed:

May 21, 1992

Appl. No.:

7/886723

Inventors:

Hugh Andrew Lagle - Raleigh NC
Duane Richard Remein - Raleigh NC
James Michael Preston - Raleigh NC
William Christian Staton - Cary NC
William B. Weeber - Apex NC

Assignee:

Alcatel Network Systems, Inc. - Richardson TX

International Classification:

H04J 300

US Classification:

370366

Abstract:

A SONET formatter circuit (10) receives a parallel STS-1** TX signal (19) from a highspeed interface module. The STS-1** TX signal (19), which contains a floating VT group payload, is demultiplexed into seven parallel VT groups (33). These seven parallel VT groups (33) are converted to serial by a parallel to serial converter (34) and transmitted serially to lowspeed interface modules as DEMUX direction VT group data signals (42, 43). The SONET formatter circuit (10) also receives serial MUX direction VT group data signals (68, 69) from lowspeed interface modules. These serial VT group data signals (68, 69) are converted to seven parallel VT groups (89) by a serial to parallel converter (64). These seven parallel VT groups (89) are multiplexed with overhead data (84) into a parallel STS-1** RX signal (50) which is transmitted to a highspeed interface module. To maintain continuous VT group frame transmissions, a VT group clock generation circuit (72) is required.

US Patent:

59387793, Aug 17, 1999

Filed:

Feb 27, 1997

Appl. No.:

8/805661

Inventors:

James M. Preston - Raleigh NC

Assignee:

Alcatel Alsthom Compagnie Generale d'Electricite - Paris

International Classification:

G01R 3128
G11C 2900

US Classification:

714718

Abstract:

ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique is a useful interface but does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. The invention provides an extension of the boundary-scan technique currently implemented to provide improved ASIC testability. The Collateral ASIC Test (method and logic) implemented in a boundary-scan device according to the invention makes possible a test process standardization to ASIC design and testing.