James Allan Schaefer

US Patent:

8429464, Apr 23, 2013

Filed:

Nov 12, 2009

Appl. No.:

12/617460

Inventors:

Ronald A. Cadima - Las Vegas NV, US
Anand Singh - Henderson NV, US
James Schaefer - Henderson NV, US

Assignee:

Bally Gaming, Inc. - Las Vegas NV

International Classification:

G06F 11/00

US Classification:

714 48

Abstract:

Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional.

US Patent:

8613663, Dec 24, 2013

Filed:

Nov 16, 2009

Appl. No.:

12/619646

Inventors:

Nathan K. Harvey - Pahrump NV, US
Pravinkumar Patel - Las Vegas NV, US
James Schaefer - Henderson NV, US
Michael N. Dubose - Henderson NV, US

Assignee:

Bally Gaming, Inc. - Las Vegas NV

International Classification:

A63F 9/24
A63F 13/00

US Classification:

463 31, 463 16, 463 20, 463 30

Abstract:

Various embodiments are directed to gaming machines having multi-monitor support for controlling up to four monitors on a gaming device. According to one embodiment, the gaming device includes a first display for presenting a primary game. The gaming device also includes a second display and a third display where the second display is positioned above the third display. The second and third displays are used in combination to present a secondary game. The gaming device further includes a multi-core processor in communication with a first video chipset and a second video chipset, wherein the first and second video chipsets support the first, second and third monitors.

US Patent:

20110119474, May 19, 2011

Filed:

Nov 16, 2009

Appl. No.:

12/619654

Inventors:

Anand Singh - Henderson NV, US
Pravinkumar Patel - Las Vegas NV, US
Darren LeBlanc - Henderson NV, US
James Schaefer - Henderson NV, US
George Mayfield - Las Vegas NV, US

Assignee:

BALLY GAMING, INC. - Las Vegas NV

International Classification:

G06F 15/177

US Classification:

713 2

Abstract:

Various embodiments disclosed herein are directed to a serial peripheral interface-based (SPI-based) BIOS system for improved upgrading of a BIOS software image in a gaming machine. The system includes a flash BIOS chip and a SPI BIOS chip. The flash BIOS chip is operable to be written to by an Intel chipset for storage of an onboard Ethernet controller's information, wherein the flash BIOS chip may contain a new BIOS software image. The SPI BIOS chip comprises a traditional BIOS including gaming extensions to the BIOS. The SPI BIOS chip can be disabled from write actions at a jumper/circuit level. When a SPI BIOS write enable jumper circuit is ON, a write protect pin of the serial peripheral interface BIOS is in the disabled state. In this regard, when the write protect pin is in the disabled state, the SPI BIOS content may be updated to the new BIOS software image from a BIOS install compact flash. When the BIOS write enable jumper circuit is OFF, the write protect pin of the serial peripheral interface BIOS is in enabled state. In this regard, when the write protect pin is in the enabled state the serial peripheral interface BIOS content cannot be updated

US Patent:

20130179738, Jul 11, 2013

Filed:

Feb 27, 2013

Appl. No.:

13/779479

Inventors:

BALLY GAMING, INC. - Las Vegas NV, US
Anand Singh - Henderson NV, US
James Schaefer - Henderson NV, US

Assignee:

BALLY GAMING, INC. - Las Vegas NV

International Classification:

G06F 11/07

US Classification:

714 54

Abstract:

Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional.

US Patent:

20140073404, Mar 13, 2014

Filed:

Nov 12, 2013

Appl. No.:

14/078386

Inventors:

Pravinkumar Patel - Las Vegas NV, US
James Schaefer - Henderson NV, US
Michael N. Dubose - Henderson NV, US

Assignee:

Bally Gaming, Inc. - Las Vegas NV

International Classification:

G07F 17/34

US Classification:

463 20, 463 25

Abstract:

Various embodiments are directed to gaming machines having multi-monitor support for controlling up to four monitors on a gaming device. According to one embodiment, the gaming device includes a first display for presenting a primary game. The gaming device also includes a second display. The second display is used to present a secondary game. The gaming device further includes a multi-core processor in communication with a first video chipset and a second video chipset, wherein the first and second video chipsets support the first and second monitors.

US Patent:

20140149676, May 29, 2014

Filed:

Jan 29, 2014

Appl. No.:

14/167035

Inventors:

- Las Vegas NV, US
Anand Singh - Henderson NV, US
James Schaefer - Henderson NV, US

International Classification:

G06F 11/07
G06F 12/12

US Classification:

711133

Abstract:

Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional.