James O Shaffer

US Patent:

7982662, Jul 19, 2011

Filed:

Dec 8, 2009

Appl. No.:

12/633652

Inventors:

James Shaffer - Boise ID, US

Assignee:

Intellex, LLC - Eagle ID

International Classification:

G01S 7/02
G01S 7/48
G01S 13/00
G01S 17/00

US Classification:

342158, 702127, 702155, 702158, 702159, 342 27, 342 52, 342 53, 342 54, 342 59, 342 70, 342 73, 342 74, 342118, 342146, 342147, 342368, 244 31, 701300, 701301, 356 3, 356 401, 356 501, 250200, 2502011, 2502031, 2502032

Abstract:

This scanning array scans an area around the array for nearby objects, collision obstructions, and terrain topography. The scanning array can scan for sounds emitted by objects in the vicinity of the scanning array, passive energy receipt sources, or it can also send out an energy beam and scan for reflections from objects within the energy beam. The energy beam can be optical, laser, radar or other energy emitting sources. The scanning array of the invention can be used for helicopter detection and avoidance of collision risk and can be used for other scanning purposes. Scanning of an entire hemisphere or greater is accomplished by manipulating the scanner platform through the coordination of either linear actuators or gimbals so as to produce nutation without rotation. This motion allows transceivers to be directly coupled to transmitting and sensing modules without the losses associated with slip rings and other coupling devices.

US Patent:

8292243, Oct 23, 2012

Filed:

Sep 3, 2009

Appl. No.:

12/553913

Inventors:

James Shaffer - Boise ID, US

Assignee:

Twin Turbine Technologies LLC - Boise ID

International Classification:

A47B 96/00

US Classification:

24822214, 403 43, 403 47, 411413

Abstract:

A compound differentially threaded element engages two or more longitudinally severed segments of a mating threaded element to provide differential linear motion. Different thread types may include pitch, thread starts, handedness or thread-form. Combinations of differential threads may be selected to enable fine or coarse linear motion without correspondingly fine or coarse thread pitches.

US Patent:

8602371, Dec 10, 2013

Filed:

Oct 12, 2012

Appl. No.:

13/651062

Inventors:

James E. Shaffer - Boise ID, US

Assignee:

Twin Turbine Technologies LLC - Boise ID

International Classification:

A47B 96/00

US Classification:

24822214, 403 43, 403 47, 411413

Abstract:

A compound differentially threaded element engages two or more longitudinally severed segments of a mating threaded element to provide differential linear motion. Different thread types may include pitch, thread starts, handedness or thread-form. Combinations of differential threads may be selected to enable fine or coarse linear motion without correspondingly fine or coarse thread pitches.

US Patent:

57985650, Aug 25, 1998

Filed:

Jan 23, 1995

Appl. No.:

8/659866

Inventors:

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Eagle ID
James M. Shaffer - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2353
H01L 2312

US Classification:

257701

Abstract:

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

US Patent:

55700322, Oct 29, 1996

Filed:

Aug 17, 1993

Appl. No.:

8/108097

Inventors:

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Eagle ID
James M. Shaffer - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 106

US Classification:

324760

Abstract:

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

US Patent:

60814632, Jun 27, 2000

Filed:

Feb 25, 1998

Appl. No.:

9/030498

Inventors:

James M. Shaffer - Boise ID
Brent Keeth - Boise ID
Eugene H. Cloud - Boise ID
Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200

Abstract:

Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.

US Patent:

6131255, Oct 17, 2000

Filed:

Aug 25, 1998

Appl. No.:

9/139452

Inventors:

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Eagle ID
James M. Shaffer - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2168

US Classification:

29 2501

Abstract:

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

US Patent:

58154272, Sep 29, 1998

Filed:

Apr 2, 1997

Appl. No.:

8/825871

Inventors:

Eugene H. Cloud - Boise ID
Brent Keeth - Boise ID
Salman Akram - Boise ID
James M. Shaffer - Boise ID
Alex Closson - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 502
G11C 506
G11C 800

US Classification:

365 51

Abstract:

A modular circuit includes a memory module that has an array of memory cells, a communication module that has communication circuitry for coupling signals between the array and external circuitry, and an interconnection module that electrically interconnects the array on the memory module and the communication circuitry on the communication module. The memory and communication modules may also be mounted to the interconnection module. Alternatively, the memory and interface modules may be electrically interconnected and mounted to each other, in which case the interconnection module is not required.