James F Walls

US Patent:

7924131, Apr 12, 2011

Filed:

May 19, 2006

Appl. No.:

11/437073

Inventors:

James A. Walls - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01F 5/00

US Classification:

336200

Abstract:

An electrical component () having an inductor includes: (a) a first substrate () comprising at least one first electrically conductive layer (); (b) one or more second substrates () comprising at least one second electrically conductive layer (); and (c) one or more electrical interconnections () electrically coupling the at least one first electrically conductive layer and the at least one second electrically conductive layer, wherein the one or more first electrically conductive layers, the one or more second electrically conductive layers and the one or more electrical interconnections are electrically coupled together to form the inductor ().

US Patent:

59267348, Jul 20, 1999

Filed:

Aug 5, 1997

Appl. No.:

8/906032

Inventors:

James Austin Walls - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 214763

US Classification:

438627

Abstract:

A semiconductor structure (10)includes a semiconductor substrate (12), a silicon layer (18)overlying the semiconductor substrate, a dielectric layer (16)overlying the silicon layer and having a contact opening to expose a portion of the silicon layer, and a metal layer stack (20)overlying the dielectric layer and having a portion in contact with the silicon layer through the contact opening. The metal layer stack comprises a barrier layer (24)of titanium with incorporated oxygen (of greater than about 11 atomic percent) to provide diffusion resistance against, for example, platinum, oxygen, and silicon.

US Patent:

20190287624, Sep 19, 2019

Filed:

Jun 14, 2018

Appl. No.:

16/008234

Inventors:

- Chandler AZ, US
James Walls - Mesa AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 16/16
G11C 16/08
G11C 16/04
G11C 16/34

Abstract:

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

US Patent:

20190206881, Jul 4, 2019

Filed:

Mar 15, 2018

Appl. No.:

15/921858

Inventors:

- Chandler AZ, US
James Walls - Mesa AZ, US
Sonu Daryanani - Tempe AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H01L 27/11517
H01L 27/105

Abstract:

A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

US Patent:

20190207006, Jul 4, 2019

Filed:

Mar 15, 2018

Appl. No.:

15/922571

Inventors:

- Chandler AZ, US
James Walls - Mesa AZ, US
Sonu Daryanani - Tempe AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H01L 29/423
H01L 27/11521

Abstract:

A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

US Patent:

20190207034, Jul 4, 2019

Filed:

Apr 17, 2018

Appl. No.:

15/955251

Inventors:

- Chandler AZ, US
James Walls - Mesa AZ, US
Sajid Kabeer - Tempe AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H01L 29/788
H01L 27/11521
H01L 29/66
H01L 21/265
H01L 21/324
H01L 21/225
H01L 29/167

Abstract:

A method is provided for forming a split-gate memory cell having field enhancement regions in the substrate for improved cell performance. The method may include forming a pair of gate structures over a substrate, performing a source implant between the pair of gate structures to form a self-aligned source implant region in the substrate, performing a field enhancement implant process to form field enhancement implant regions, e.g., having an opposite dopant polarity as the source implant, at or adjacent lateral sides of the source implant region, and diffusing the source implant region and field enhancement implant regions to thereby define a source region with field enhanced regions at lateral edges of the source region. The field enhanced implant process may include at least one non-vertical angled implant.

US Patent:

20160315257, Oct 27, 2016

Filed:

Jul 1, 2016

Appl. No.:

15/200322

Inventors:

- Chandler AZ, US
James Walls - Mesa AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H01L 45/00
H01L 27/24

Abstract:

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

US Patent:

20160190442, Jun 30, 2016

Filed:

Mar 9, 2016

Appl. No.:

15/065354

Inventors:

- Chandler AZ, US
James Walls - Mesa AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H01L 45/00
H01L 27/24

Abstract:

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.