James Michael Wiley

US Patent:

6381358, Apr 30, 2002

Filed:

Apr 27, 2000

Appl. No.:

09/559512

Inventors:

Anthony Vacca - Ceder Park TX
Thomas Vavul - San Francisco CA
Donald J. Parker - San Jose CA
Zain Saidin - Sunnyvale CA
Sterling G. Watson - Palo Alto CA
James N. Wiley - Menlo Park CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

G06K 900

US Classification:

382145, 382144, 348 86

Abstract:

A method and software program for determining printability of a defect on a reticle or photomask onto a substrate during processing. That is performed by creating a pixel grid image having a plurality of individual pixel images showing the defect. A gray scale value is assigned to each pixel image of the pixel grid image and a probable center pixel of the defect is selected. Then the polarity of the defect is determined, with a coarse center pixel of the defect optionally selected using the probable center defect and polarity of the defect. If a coarse center pixel is selected, then a fine center of the defect can optionally be selected from the coarse center pixel and polarity of the defect. From the center pixel the physical extent of the defect can be determined followed by the determination the transmissivity energy level of the physical extent of the defect. Optionally, the proximity of the defect to a pattern edge on the reticle or photomask can be determined using the physical extent and polarity of the defect.

US Patent:

6516085, Feb 4, 2003

Filed:

May 3, 1999

Appl. No.:

09/304437

Inventors:

James N. Wiley - Menlo Park CA
Jun Ye - Palo Alto CA
David S. Alles - Los Altos CA
Yen-Wen Lu - Los Altos CA
Yu Cao - Sunnyvale CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G06K 900

US Classification:

382144, 348 87

Abstract:

Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.

US Patent:

6529621, Mar 4, 2003

Filed:

Dec 17, 1998

Appl. No.:

09/213744

Inventors:

Lance A. Glasser - Saratoga CA
Jun Ye - Palo Alto CA
David S. Alles - Los Altos CA
James N. Wiley - Menlo Park CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G06K 900

US Classification:

382144, 382147, 382149, 348 92, 348 87

Abstract:

A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

US Patent:

6654489, Nov 25, 2003

Filed:

Dec 4, 2002

Appl. No.:

10/314030

Inventors:

James N. Wiley - Menlo Park CA
Jun Ye - Palo Alto CA
David S. Alles - Los Altos CA
Yen-Wen Lu - Los Altos CA
Yu Cao - Sunnyvale CA

Assignee:

KLA-Tencor Technologies Corporation - San Jose CA

International Classification:

G06K 900

US Classification:

382144, 348 87

Abstract:

Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.

US Patent:

6748103, Jun 8, 2004

Filed:

Feb 4, 2003

Appl. No.:

10/359444

Inventors:

Lance A. Glasser - Saratoga CA
Jun Ye - Palo Alto CA
David S. Alles - Los Altos CA
James N. Wiley - Menlo Park CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G06K 900

US Classification:

382149, 382147

Abstract:

A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

US Patent:

7138640, Nov 21, 2006

Filed:

Oct 16, 2003

Appl. No.:

10/688839

Inventors:

Gil Delgado - Livermore CA, US
John McMurtry - Menlo Park CA, US
James Wiley - Menlo Park CA, US

Assignee:

KLA-Tencor Technologies, Corporation - Milpitas CA

International Classification:

G01J 1/42

US Classification:

250372

Abstract:

The invention pertains to mechanisms for protecting surfaces of optical components of an optical inspection system. One aspect of the invention relates to a gas purge system that produces a gas stream that blocks contaminants from reaching the optical surfaces of the optical components and that transports contaminants away from the optical surfaces of the optical components. Another aspect of the invention relates to a transparent cover that physically blocks contaminants from reaching the optical surfaces of the optical components. Yet another aspect of the invention relates to a combination of the gas purge system and the transparent cover.

US Patent:

7695876, Apr 13, 2010

Filed:

Aug 24, 2006

Appl. No.:

11/466978

Inventors:

Jun Ye - Palo Alto CA, US
Moshe E. Preil - Sunnyvale CA, US
Xun Chen - Palo Alto CA, US
James Wiley - Menlo Park CA, US

Assignee:

Brion Technologies, Inc. - Santa Clara CA

International Classification:

G03F 9/00
G03C 5/00

US Classification:

430 30, 382145, 382147, 382149

Abstract:

A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

US Patent:

7853920, Dec 14, 2010

Filed:

May 19, 2006

Appl. No.:

11/437594

Inventors:

Moshe E. Preil - Sunnyvale CA, US
Jun Ye - Palo Alto CA, US
James N. Wiley - Menlo Park CA, US
Michael J. Gassner - San Jose CA, US

Assignee:

ASML Netherlands B.V. - Veldhoven

International Classification:

G06F 17/50
G06K 9/00

US Classification:

716 21, 716 19, 382149, 430 30

Abstract:

One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.