Khee Yong Lim - Singapore, SG Victor Chan - Newburgh NY, US Eng Hua Lim - Singapore, SG Wenhe Lin - Singapore, SG Jamin F. Fen - Wappingers Falls NY, US
Assignee:
GLOBALFOUNDRIES Singapore Pte. Ltd. - Singapore
International Classification:
H01L 21/336 H01L 21/8234
US Classification:
438199, 257369, 257E21633
Abstract:
A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
Double Anneal With Improved Reliability For Dual Contact Etch Stop Liner Scheme
Khee Lim - Singapore, SG Victor Chan - Newburgh NY, US Eng Lim - Singapore, SG Wenhe Lin - Singapore, SG Jamin Fen - Wappingers Falls NY, US
International Classification:
H01L 21/8238 H01L 29/78
US Classification:
257369000, 438199000, 438233000
Abstract:
A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
Integrated Circuit System Having Strained Transistor
Young Way Teh - Singapore, SG Xiangdong Chen - Poughquag NY, US Jamin F. Fen - Wappingers Falls NY, US Jun Jung Kim - Fishkill NY, US Daewon Yang - Hopewell Junction NY, US Roman Knoefler - Dresden, DE Michael P. Belyansky - Bethel CT, US
Assignee:
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. - Singapore INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY SAMSUNG - Gyeonggi-do INFINEON TECHNOLOGIES NORTH AMERICA CORP. - San Jose CA
International Classification:
H01L 27/092
US Classification:
257369, 257E27062
Abstract:
An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.