Janet M Olson

US Patent:

20180107777, Apr 19, 2018

Filed:

Oct 17, 2016

Appl. No.:

15/295837

Inventors:

- Mountain View CA, US
Jovanka Ciric Vujkovic - Mountain View CA, US
Van E. Morgan - Phoenixville PA, US
Janet L. Olson - Saratoga CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

Abstract:

Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.