Jang W Kim

US Patent:

7853908, Dec 14, 2010

Filed:

Sep 5, 2007

Appl. No.:

11/899215

Inventors:

Jang Dae Kim - San Jose CA, US
Steve A. Martinez - Tucson AZ, US
Satya N. Mishra - Fort Collins CO, US
Alan P. Bucholz - Fort Collins CO, US
Hui X. Li - Antioch CA, US
Rajesh R. Berigei - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 4, 716 6, 716 18, 703 3, 703 13, 703 14, 714740, 714741

Abstract:

An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

US Patent:

8001515, Aug 16, 2011

Filed:

Dec 21, 2007

Appl. No.:

12/004862

Inventors:

Jang Dae Kim - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716132, 716106, 703 2

Abstract:

An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a ‘golden’ reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs. The cost surface modeling with a Latin Hypercube Sampling design-of-experiment provides a statistical mathematical approximation of the actual design's error cost surface, speeding up the optimization by replacing the costly simulation of the actual design with mere evaluation of the mathematical cost surface model expression.

US Patent:

8350632, Jan 8, 2013

Filed:

Nov 5, 2009

Appl. No.:

12/590310

Inventors:

Jang Dae Kim - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03B 5/18

US Classification:

331117FE, 331117 R

Abstract:

A dipole oscillation tank circuit includes a first capacitive structure, an inductive structure, and a second capacitive structure connected in series. The tank circuit transfers electric energy back and forth between the capacitive structures in dipole oscillation cycles. A renewal circuit injects energy into the tank circuit to replenish energy lost during the oscillation cycles. A switch is connected in parallel across the first capacitive structure and in parallel across the inductive structure and the second capacitive structure. During one phase of the oscillation cycles, the switch is opened for current to flow through the first capacitive structure and the inductive structure, and then closed to bypass the first capacitive structure. During another phase of the oscillation cycles, the switch is closed to bypass the first capacitive structure and then opened for current to flow through the first capacitive structure and the inductive structure.

US Patent:

8412155, Apr 2, 2013

Filed:

Jul 28, 2011

Appl. No.:

13/193541

Inventors:

Philip McCanna - Sunnyvale CA, US
Nesrin Umur - San Francisco CA, US
Jonathan Mason - San Francisco CA, US
Colleen Twitty - San Francisco CA, US
Jang Kim - San Francisco CA, US

Assignee:

Boku, Inc. - San Francisco CA

International Classification:

H04M 11/00

US Classification:

455407, 705 261, 455410, 455421

Abstract:

Systems and methods to accelerate transactions made via mobile communications. In one aspect, a system includes: a data storage facility to store information associated with past payment transactions and an interchange coupled with the data storage facility. The interchange includes a common format processor and a plurality of converters to interface with a plurality of controllers. The converters are configured to communicate with the controllers in different formats, and to communicate with the common format processor in a common format. The common format processor includes a risk engine and a transaction engine. The risk engine estimates a risk in a billing process; and the transaction engine determines whether or not to notify a merchant of the predicted result of billing based on the suggestion from the risk engine and/or other information, such as the status of the wireless telecommunications network.

US Patent:

20120326618, Dec 27, 2012

Filed:

Jun 24, 2011

Appl. No.:

13/168260

Inventors:

Jang Dae Kim - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H05B 37/02

US Classification:

315224

Abstract:

In accordance with the presently claimed invention, circuitry and a method are provided for using a voltage to drive a light emitting diode (LED) load including one or more LEDs. The incoming voltage is switched and inductively conditioned to drive the LED load in such a manner as to cause the LED load to appear as a substantially linear resistive load, thereby maximizing the power factor presented to an AC power grid serving as the source of the input voltage.

US Patent:

20130015820, Jan 17, 2013

Filed:

Jul 12, 2011

Appl. No.:

13/180963

Inventors:

Jang Dae Kim - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H02J 7/00

US Classification:

320128

Abstract:

System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

US Patent:

20130015821, Jan 17, 2013

Filed:

Dec 23, 2011

Appl. No.:

13/336695

Inventors:

Jang Dae KIM - San Jose CA, US
Jacek Justyn Marcinkowski - San Pedro CA, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H02J 7/00

US Classification:

320128

Abstract:

System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and capacitive load switched-mode power supplies. The switched-mode power supplies transfer the electrical energy between the load capacitors and the differential power buses to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

US Patent:

20230056231, Feb 23, 2023

Filed:

Nov 22, 2021

Appl. No.:

17/532826

Inventors:

- Gyeonggi-do, KR
Jang Ryul KIM - San Jose CA, US

International Classification:

G11C 29/42
G11C 29/12
G11C 29/00
G11C 7/10

Abstract:

A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.