Jarie G Bolander

US Patent:

7055121, May 30, 2006

Filed:

Sep 26, 2002

Appl. No.:

10/256502

Inventors:

Jarie Bolander - Redwood City CA, US
Steven P. Larky - Del Mar CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 11, 716 4, 716 6, 716 10

Abstract:

A method, system, and computer program product for designing an integrated circuit. In one example, a standard library is provided having a plurality of standard circuit cells, and a substitute library is provided having a plurality of substitute circuit cells wherein one or more substitute circuit cells correspond to one or more standard circuit cells and the one or more substitute circuit cells have at least one differing electrical characteristic—such as power consumption, quiescent current consumption, speed/response time, leakage current, etc. —than the corresponding one or more standard circuit cells. An initial circuit design is created using the plurality of standard circuit cells of the standard library; and one or more non-critical timing paths are identified in the initial circuit design, the non-critical timing paths including one or more standard circuit cells. The one or more standard circuit cells in at least one of the non-critical timing paths of the initial circuit design are replaced with one or more substitute circuit cells to form a modified integrated circuit design. The replacement operation may occur after standard circuit cells of the initial circuit design have been placed and routed.

US Patent:

7257504, Aug 14, 2007

Filed:

Jun 3, 2005

Appl. No.:

11/145016

Inventors:

Jarie G. Bolander - San Francisco CA, US
Forrest Wunderlich - El Granada CA, US
Neil Jarvis - Saratoga CA, US
Christopher J. Lee - Santa Clara CA, US
Bernard Baron - Mountain View CA, US
Paul A. Lovoi - Saratoga CA, US

Assignee:

Tagent Corporation - Sunnyvale CA

International Classification:

H04B 1/59
H04Q 5/22

US Classification:

702106, 340 1052, 702 85, 702 72, 702 75, 324763, 324764, 324 76, 438 14, 438 17, 438 18, 455 412, 4551512

Abstract:

A radio frequency ID tag, very small in size and with an onboard antenna, is manufactured, tested and applied cost-efficiently. The transmit frequency for the tag is set during manufacture approximately, within a selected range, in a gross tuning step. A second tuning step fine tunes each tag by RF communication to set values of capacitance, resistance, etc. , and this can be at the point of application of the tags. Other aspects include burning a randomly-selected value in the RF ID chip during manufacture to impose a random time delay for tag response (rather than having a random generator on the chip itself); structural testing of a large number of tags on a wafer using on-wafer interconnects and a special onboard sequencer test die; and production of the tag so as to be tunable to different frequency ranges.

US Patent:

7317378, Jan 8, 2008

Filed:

Aug 17, 2004

Appl. No.:

10/919800

Inventors:

Neil Jarvis - Saratoga CA, US
Paul A. Lovoi - Saratoga CA, US
Warren Fay - San Jose CA, US
Christopher J. Lee - Santa Clara CA, US
Jarie G. Bolander - Redwood City CA, US
Bernard Baron - Mountain View CA, US
Anthony G. Jennetti - Sunnyvale CA, US
Forrest Wunderlich - El Granada CA, US
Oscar Ayzenberg - Cupertino CA, US

Assignee:

Tagent Corporation - Sunnyvale CA

International Classification:

H04Q 1/00

US Classification:

340 101, 3405721, 340 103

Abstract:

An electronic identification tag, usually in very small size, responds to a reader with an identification code unique to the object to which the tag is attached. The stand-alone device responds to a reader signal by storing energy received from the signal, then using the stored energy to generate another signal that is encoded with identification information. In operation, a reader generates RF energy which can reach a multiplicity of such tags over a distance of several meters. The system minimizes power requirements for the tag by minimizing intelligence in the IC. Use of a transmit frequency which is different from the reader's power frequency reduces interference between the power pulse and information pulse, eliminates the need for filters and enables the multiplied clock reference frequency as the transmit carrier frequency.

US Patent:

7667603, Feb 23, 2010

Filed:

Apr 13, 2006

Appl. No.:

11/404567

Inventors:

Jarie G. Bolander - San Francisco CA, US
Paul A. Lovoi - Saratoga CA, US
Teri E. Judelson - Saratoga CA, US
Geoff A. Zawolkow - San Carlos CA, US

Assignee:

Tagent Corporation - Sunnyvale CA

International Classification:

G08B 13/14

US Classification:

3405724, 3405721, 34053913

Abstract:

RFID tags of very small size are embedded in products or composed of products in a manufacturing process. The system employs different read and write modes to enable auto-tracking of material, some assembly, assembly and component items through various stages of the manufacturing process. As each item passes special predetermined points in the manufacturing process, the embedded tag is activated and placed in track mode. The tag transmits its ID and a track count representing the number of stations passed. The tag's track count is incremented and the updated track count is stored in non-volatile memory in the tag. The tags can be programmed so that once the count exceeds a predetermined count, a status bit is set in the tag's memory indicating that the item has been completely through the manufacturing process. Thus, the system can determine whether an item or product has been completed. After manufacture the same RFID tag can be used for tracking, inventory and item authentication.

US Patent:

7812725, Oct 12, 2010

Filed:

Dec 21, 2006

Appl. No.:

11/644075

Inventors:

Jarie G. Bolander - San Francisco CA, US
Paul A. Lovoi - Saratoga CA, US
Geoff A. Zawolkow - San Carlos CA, US

Assignee:

Tagent 6 Corporation - Mountain View CA

International Classification:

G08B 13/14

US Classification:

3405721, 340 101, 34053921, 34082569

Abstract:

A system for tracking items using passive RFID tags utilizes separate data and power frequencies. Within an area in which the items are located, one or more data readers are provided but many more separate power modules are distributed through the space, for powering up the tags. With the power nodes distributed, the tags are powered from a relatively short distance, enabling the tags to transmit through a greater distance. One or more of the readers can include a power-node control which sends an RF signal to control on/off status of specific power nodes within the area, so that power nodes can be activated zone by zone, to thereby permit the reader to determine location by zone of products as their RFID tags are read.

US Patent:

20120001646, Jan 5, 2012

Filed:

Jun 30, 2011

Appl. No.:

13/173621

Inventors:

Jarie BOLANDER - San Francisco CA, US
Keith FIFE - Palo Alto CA, US
Mark MILGREW - Branford CT, US

Assignee:

LIFE TECHNOLOGIES CORPORATION - CARLSBAD CA

International Classification:

G01R 27/26
G01R 27/08
H01L 23/544

US Classification:

324679, 257 48, 324705, 257253, 257E23179

Abstract:

The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.

US Patent:

20120025985, Feb 2, 2012

Filed:

Jul 12, 2011

Appl. No.:

13/135716

Inventors:

Jarie G. Bolander - San Francisco CA, US
Forrest Wunderlich - El Granada CA, US
Daniel Paley - Redwood City CA, US

International Classification:

G08B 13/14

US Classification:

3405721

Abstract:

Miniature RFID tags are used in a system for identifying, locating, tracking and inventorying patient specimens pursuant to medical testing. The RFID tags are attached to specimen vessels, and at a point of collection for patient specimens each RFID tag of a vessel is associated with patient and test data, in a collection site database. When a series of vessels are to go to a laboratory, a hand-held device receives all data on the specimens via download from the collection site PC/database. A courier picks up a container with the specimen vessels and delivers it to the laboratory, along with the hand-held device. At the lab a reader reads all specimen tags, and the data stored in the hand-held device is downloaded to a lab processor/database to verify all specimens are present. Location of specimens can be done by reading or powering up different zones, and the hand-held device can have a power node for selectively powering one or several specimen tags for identification or location of specific specimens.

US Patent:

6825683, Nov 30, 2004

Filed:

Apr 18, 2002

Appl. No.:

10/125117

Inventors:

Paul D. Berndt - Woodinville WA
Jarie G. Bolander - Redwood City CA
Leah S. Clark - San Diego CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G10R 3102

US Classification:

324763, 324765

Abstract:

In one embodiment, a test circuit is coupled to receive a first signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package. In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone. In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both.