Jason William Brandt

US Patent:

7743233, Jun 22, 2010

Filed:

Apr 5, 2005

Appl. No.:

11/100032

Inventors:

Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Richard A. Hankins - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Jason W. Brandt - Austin TX, US
Prashant Sethi - Folsom CA, US
Douglas M. Carmean - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Ryan N. Rakvic - Palo Alto CA, US
John L. Reid - Portland OR, US
David K. Poulsen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
James Paul Held - Portland OR, US
James Charles Abel - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712220

Abstract:

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

US Patent:

8447962, May 21, 2013

Filed:

Dec 22, 2009

Appl. No.:

12/644440

Inventors:

Christopher J. Hughes - Cupertino CA, US
Mayank Bomb - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
Mark J. Buxton - Chandler AZ, US
Mark J. Charney - Lexington MA, US
Srinivas Chennupaty - Portland OR, US
Jesus Corbal - Barcelona, ES
Martin G. Dixon - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki (Saito) Ido - Sunnyvale CA, US
Peter Lachner - Heroldstatt, DE
Gilbert Neiger - Portland OR, US
Chris J. Newburn - South Beloit IL, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Bret L. Toll - Hillsboro OR, US
Robert Valentine - Kiryat Tivon, IL
Jeffrey G. Wiedemeier - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712244

Abstract:

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

US Patent:

20110153990, Jun 23, 2011

Filed:

Dec 23, 2009

Appl. No.:

12/646762

Inventors:

Guilherme D. Ottoni - Cambell CA, US
Hong Wang - Santa Clara CA, US
Christopher T. Weaver - Austin TX, US
Thomas A. Hartin - Austin TX, US
Wei Li - Santa Clara CA, US
Jason W. Brandt - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38

US Classification:

712208, 712225, 712234, 712E09016, 712E09045

Abstract:

An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality of condition code bits from a first register to a second register.

US Patent:

20220207154, Jun 30, 2022

Filed:

Dec 26, 2020

Appl. No.:

17/134333

Inventors:

- Santa Clara CA, US
Mohammad Reza Haghighat - San Jose CA, US
Asit Mallick - Saratoga CA, US
Alaa Alameldeen - Hillsboro OR, US
Abhishek Basak - Bothell WA, US
Jason W. Brandt - Austin TX, US
Michael Chynoweth - Placitas NM, US
Carlos Rozas - Portland OR, US
Scott Constable - Portland OR, US
Martin Dixon - Portland OR, US
Matthew Fernandez - Beaverton OR, US
Fangfei Liu - Hillsboro OR, US
Francis McKeen - Portland OR, US
Joseph Nuzman - Haifa, IL
Gilles Pokam - Livermore CA, US
Thomas Unterluggauer - Hillsboro OR, US
Xiang Zou - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 21/60
H04L 9/08
H04L 9/30

Abstract:

Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

US Patent:

20230099517, Mar 30, 2023

Filed:

Dec 23, 2021

Appl. No.:

17/561452

Inventors:

- Santa Clara CA, US
Asit Mallick - Saratoga CA, US
Rajesh Sankaran - Portland OR, US
Hisham Shafi - Akko, IL
Vedvyas Shanbhogue - Austin TX, US
Jason Brandt - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/48
G06F 9/54
G06F 9/30

Abstract:

Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

US Patent:

20190205061, Jul 4, 2019

Filed:

Dec 29, 2017

Appl. No.:

15/858878

Inventors:

- Santa Clara CA, US
Alexander Gendler - Kiriat Motzkin, IL
Efraim Rotem - Haifa, IL
Moshe Cohen - Zichron Yaakov, IL
Asit K. Mallick - Saratoga CA, US
Jason W. Brandt - Austin TX, US
Kameswar Subramaniam - Austin TX, US
Nathan Fellman - Kiryat Motzkin, IL
Hisham Shafi - Akko, IL

International Classification:

G06F 3/06
G06F 9/30

Abstract:

Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

US Patent:

20190041950, Feb 7, 2019

Filed:

Mar 28, 2018

Appl. No.:

15/938268

Inventors:

- Santa Clara CA, US
Rajshree Chabukswar - Sunnyvale CA, US
Eliezer Weissmann - Haifa, IL
Jason W. Brandt - Austin TX, US
Alexander Gendler - Kiriat Motzkin, IL
Ahmad Yasin - Haifa, IL
Patrick Konsor - Hillsboro OR, US
Sneha Gohad - San Jose CA, US
William Freelove - Hillsboro OR, US

International Classification:

G06F 1/32
G06F 12/1045
G06F 11/34

Abstract:

In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.

US Patent:

20180150301, May 31, 2018

Filed:

May 20, 2013

Appl. No.:

13/898189

Inventors:

- Santa Clara CA, US
Yen-Kuang (Y.K.) Chen - Cupertino CA, US
Mayank Bomb - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
Mark J. Buxton - Chandler AZ, US
Mark J. Charney - Lexington MA, US
Srinivas Chennupaty - Portland OR, US
Jesus Corbal - Barcelona, ES
Martin G. Dixon - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki (Saito) Ido - Sunnyvale CA, US
Peter Lachner - Heroldstatt, DE
Gilbert Neiger - Portland OR, US
Chris J. Newburn - South Beloit IL, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Bret L. Toll - Hillsboro OR, US
Robert Valentine - Qiryat Tivon, IL
Jeffrey G. Wiedemeier - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.