Jason A Goldstein

US Patent:

7481134, Jan 27, 2009

Filed:

Oct 30, 2006

Appl. No.:

11/589504

Inventors:

Jason Goldstein - Merrimack NH, US

Assignee:

Brookstone Purchasing, Inc. - Merrimack NH

International Classification:

B67B 7/44
B67B 7/04

US Classification:

81 329, 7155

Abstract:

A bottle opener has a holding body that holds the top of the container. The holding body has a support that contacts the container and a gripping member opposite the support. The gripping member moves relative to the support between a released position, in which the gripping member permits the container to be released from the device, and an engaged position, in which the gripping member causes the container to be held between the gripping member and the support. The bottle opener also has an extracting element, such as a corkscrew, operably connected to the holding body which extracts the stopper from the container. The bottle opener has an integrated cutter positioned on at least one of the support and the gripping member, the cutter being adapted to cut the wrapper.

US Patent:

8449842, May 28, 2013

Filed:

Mar 11, 2010

Appl. No.:

12/722211

Inventors:

Kevin J. Knopp - Newburyport MA, US
Daryoosh Vakhshoori - Cambridge MA, US
Peidong Wang - Carlisle MA, US
Masud Azimi - Belmont MA, US
Scott E. Miller - Somerville MA, US
Jason Goldstein - Salem NH, US
Stephen McLaughlin - Andover MA, US

Assignee:

Thermo Scientific Portable Analytical Instruments Inc. - Tewksbury MA

International Classification:

A61B 10/00

US Classification:

422536, 422 50, 422500, 422501, 422502, 436180

Abstract:

Systems and methods disclosed include: a support apparatus configured to detachably receive a chip; movable pins extendible from a first position to a second position, where, in the first position, the movable pins do not contact a chip positioned on the support apparatus, and in the second position, the movable pins contact electrical terminals of a heating element within a chip positioned on the support apparatus; a radiation source configured to direct radiation to be incident on a chip positioned on the support apparatus; a detector; and an electronic processor, the electronic processor being configured to detect molecules in a sample positioned within the chip, and to determine a temperature of the chip by measuring an electrical resistance between two of the multiple pins connected to the electrical terminals.

US Patent:

20040098517, May 20, 2004

Filed:

Jul 2, 2003

Appl. No.:

10/612863

Inventors:

Jason Goldstein - Brookline MA, US

International Classification:

G06F003/00

US Classification:

710/001000

Abstract:

A serial-to-parallel/parallel-to-serial conversion engine provides a bi-directional interface between a serial TDM highway and a parallel TDM highway. The conversion engine includes a serial-to-parallel data conversion device receives a serially received data word and provides a parallel output data word. The conversion engine includes a serial data input interface that receives the serially received data word and provides a received data word. A serial-to-parallel mapping circuit receives the received data word and generates memory write control and write address signals. A memory device includes a first port responsive to the memory write control signals and write address signals for writing the received data word into the memory device, and a second port responsive to memory read control and read address signals for reading data from the memory device. Output interface circuitry generates the memory read control and read address signals, and receives output data from the memory device and reorders the bits of the parallel output data to provide the parallel data word. The conversion engine also includes a parallel-to-serial conversion device that receives a parallel received data word and provides a serial data word. The parallel-to-serial conversion device includes a memory device having a first port responsive to memory write control and write address signals, and a second port responsive to memory read control and read address signals. A parallel-to-serial mapping circuit receives the parallel received data word and generates the memory write control and write address signals to write a bit shuffled version of the parallel received data word into the memory device. A data output interface generates the memory read control and read address signals to perform reads from the memory device and receives output data from the memory device to provide the serial data word.

US Patent:

20060001683, Jan 5, 2006

Filed:

Mar 23, 2005

Appl. No.:

11/087423

Inventors:

Alexander May - Stoneham MA, US
Jason Goldstein - Redmond WA, US

International Classification:

G09G 5/00

US Classification:

345661000

Abstract:

Methods and apparatus, including computer program products, for structure image generation. A network includes a corporate server linked to a building server, devices linked to the building server, a first set of the devices selectively controlling room light emanating to an exterior of a structure from a plurality of rooms within the structure, and a second set of devices selectively controlling lighting fixtures within the plurality of rooms, the first set of devices integrated with the second set of devices.

US Patent:

6684275, Jan 27, 2004

Filed:

Oct 23, 1999

Appl. No.:

09/427669

Inventors:

Jason A. Goldstein - Brookline MA

Assignee:

Octave Communications, Inc. - Salem NH

International Classification:

G06F 1312

US Classification:

710 71, 710 2, 341100

Abstract:

A serial-to-parallel/parallel-to-serial conversion engine provides a bi-directional interface between a serial TDM highway and a parallel TDM highway. The conversion engine includes a serial-to-parallel data conversion device receives a serially received data word and provides a parallel output data word. The conversion engine includes a serial data input interface that receives the serially received data word and provides a received data word. A serial-to-parallel mapping circuit receives the received data word and generates memory write control and write address signals. A memory device includes a first port responsive to the memory write control signals and write address signals for writing the received data word into the memory device, and a second port responsive to memory read control and read address signals for reading data from the memory device. Output interface circuitry generates the memory read control and read address signals, and receives output data from the memory device and reorders the bits of the parallel output data to provide the parallel data word. The conversion engine also includes a parallel-to-serial conversion device that receives a parallel received data word and provides a serial data word.