Jason T Varricchione

US Patent:

7173501, Feb 6, 2007

Filed:

May 14, 2004

Appl. No.:

10/845661

Inventors:

Jason Varricchione - Williston VT, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03L 1/00

US Classification:

331176, 331 66, 327 83

Abstract:

An oscillator circuit () can provide a dual slop temperature response. For a lower temperature range, a capacitor () can be charged and/or discharged according to a first current source () that provides an essentially constant current source. For a higher temperature range, the capacitor () can be charged and/or discharged according to a second current source () that can be enabled and/or provide current according to a voltage proportional to absolute temperature. A slightly positive temperature coefficient of a first current source () can be offset by a threshold detect circuit ( and ) within a second comparator circuit () that utilizes the threshold voltage (Vt) of a transistor () as a low limit for a capacitor voltage.

US Patent:

7728638, Jun 1, 2010

Filed:

Apr 25, 2008

Appl. No.:

12/109609

Inventors:

Jason Varricchione - Williston VT, US

Assignee:

Qimonda North America Corp. - Cary NC

International Classification:

H03L 7/06

US Classification:

327158, 327149

Abstract:

One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.

US Patent:

8467254, Jun 18, 2013

Filed:

Sep 25, 2011

Appl. No.:

13/244609

Inventors:

Jason Varricchione - Williston VT, US
Stephen Potvin - Winooski VT, US

Assignee:

Nanya Technology Corporation - Taoyuan

International Classification:

G11C 7/06

US Classification:

36518907, 36518905, 365191, 365194

Abstract:

A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.

US Patent:

20020196693, Dec 26, 2002

Filed:

Jun 25, 2001

Appl. No.:

09/891025

Inventors:

Claude Bertin - South Burlington VT, US
John Atkinson - Underhill VT, US
Nicholas Van Heel - Eagle ID, US
Jason Varricchione - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C005/00

US Classification:

365/225700

Abstract:

A universal fuse latch device comprises a latch circuit receiving a precharge signal and latching the precharge signal at a latch node thereof for initializing the latch to a first state; and one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state, and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate programming of one of the fuse and anti-fuse type element. In one application, the universal fuse latch device is implemented as part of a programmable fuse bank comprising a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is provided that is programmed in accordance with a priority of legs to be interrogated in the information fuse latches. The system and method of the invention implements logic circuits and devices for determining the priority of legs that are to be interrogated for accessing the redundancy information and for generating appropriate interrogation strobe and leg selection signals to enable proper interrogation of the information fuse latches according to the determined priority.

US Patent:

20090122856, May 14, 2009

Filed:

Nov 8, 2007

Appl. No.:

11/936829

Inventors:

Robert BAXTER - Chapel Hill NC, US
Roland BARTH - Ottobrunn, DE
Steve BOWYER - Raleigh NC, US
Jonghee HAN - Cary NC, US
Harald LORENZ - South Burlington VT, US
Jason VARRICCHIONE - Williston VT, US
Thomas VOGELSANG - Jericho VT, US

International Classification:

H03K 7/04

US Classification:

375239

Abstract:

A method and apparatus for reducing the number of DQ pins and current used to access data in a memory system or data transfer device, wherein an additional bit is temporally encoded on a data word during a singular access cycle. During an access cycle, the pulse level or levels of encoded bits may determine one or more bits values in a data word being expressed, while the pulse/pulses position in time within a data access cycle determines the remaining bits.