Jason Michael Walter

US Patent:

20210408355, Dec 30, 2021

Filed:

Sep 13, 2021

Appl. No.:

17/472821

Inventors:

- Elmsford NY, US
Denis Amparo - White Plains, PH
Oleksandr Chernyashevskyy - White Plains NY, US
Oleg Mukhanov - Putnam Valley NY, US
Mario Renzullo - Yonkers NY, US
Igor Vernik - Yorktown Heights NY, US
John Vivalda - Poughkeepsie NY, US
Jason Walter - Trumbull CT, US

International Classification:

H01L 39/04
H01L 23/00
H01L 39/22
H01L 39/24

Abstract:

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

US Patent:

20200119251, Apr 16, 2020

Filed:

Oct 11, 2019

Appl. No.:

16/599985

Inventors:

- Elmsford NY, US
Denis Amparo - White Plains, PH
Oleksandr Chernyashevskyy - White Plains NY, US
Oleg Mukhanov - Putnam Valley NY, US
Mario Renzullo - Yonkers NY, US
Igor Vernik - Yorktown Heights NY, US
John Vivalda - Poughkeepsie NY, US
Jason Walter - Trumbull CT, US

International Classification:

H01L 39/04
H01L 23/00
H01L 39/22
H01L 39/24

Abstract:

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.