Jason Y Zhang

US Patent:

20120223321, Sep 6, 2012

Filed:

Mar 22, 2011

Appl. No.:

13/053556

Inventors:

Heny Lin - Irvine CA, US
Jason Zhang - Monterey Park CA, US
Alberto Guerra - Palos Verdes Estates CA, US

Assignee:

INTERNATIONAL RECTIFIER CORPORATION - El Segundo CA

International Classification:

H01L 29/12

US Classification:

257 76, 257E29068

Abstract:

One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

US Patent:

20120223322, Sep 6, 2012

Filed:

Mar 22, 2011

Appl. No.:

13/053646

Inventors:

Heny Lin - Irvine CA, US
Jason Zhang - Monterey Park CA, US
Alberto Guerra - Palos Verdes Estates CA, US

Assignee:

INTERNATIONAL RECTIFIER CORPORATION - El Segundo CA

International Classification:

H01L 29/20

US Classification:

257 76, 257E29089

Abstract:

One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.