Jeanette Luree Roberts

US Patent:

20200364600, Nov 19, 2020

Filed:

Dec 29, 2017

Appl. No.:

16/766411

Inventors:

- Santa Clara CA, US
Shawna M. Liff - Scottsdale AZ, US
Jeanette M. Roberts - North Plains OR, US
James S. Clarke - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06N 10/00
H01L 21/48
H01L 39/02
H01L 27/18
H01L 39/24

Abstract:

Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.

US Patent:

20190043919, Feb 7, 2019

Filed:

Jun 20, 2018

Appl. No.:

16/012815

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
Lester Lampert - Portland OR, US
James S. Clarke - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Zachary R. Yoscovits - Beaverton OR, US
Nicole K. Thomas - Portland OR, US
Roman Caudillo - Portland OR, US
Kanwaljit Singh - Rotterdam, NL
David J. Michalak - Portland OR, US
Jeanette M. Roberts - North Plains OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/18
H01L 39/22
H01L 49/02
G06N 99/00

Abstract:

Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

US Patent:

20190044044, Feb 7, 2019

Filed:

Feb 15, 2018

Appl. No.:

15/897712

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
James S. Clarke - Portland OR, US
Jeanette M. Roberts - North Plains OR, US
Ravi Pillarisetty - Portland OR, US
David J. Michalak - Portland OR, US
Kanwaljit Singh - Rotterdam, NL
Roman Caudillo - Portland OR, US
Zachary R. Yoscovits - Beaverton OR, US
Nicole K. Thomas - Portland OR, US
Hubert C. George - Portland OR, US
Stefano Pellerano - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 39/02
H01L 39/22

Abstract:

Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.

US Patent:

20190006572, Jan 3, 2019

Filed:

Jun 29, 2017

Appl. No.:

15/637682

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
Johanna M. Swan - Scottsdale AZ, US
Shawna M. Liff - Scottsdale AZ, US
Ye Seul Nam - Chandler AZ, US
James S. Clarke - Portland OR, US
Jeanette M. Roberts - North Plains OR, US
Roman Caudillo - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 39/04
H01L 25/16
H01L 23/538
H01L 23/66
H01L 23/552
H01L 39/02
H01L 39/24
H01P 3/08
H01P 11/00
H05K 1/02
G06N 99/00

Abstract:

Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.