Jeff A Mcclain

US Patent:

6430081, Aug 6, 2002

Filed:

Aug 30, 2001

Appl. No.:

09/943396

Inventors:

Jeff A. McClain - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1124

US Classification:

365149, 365 51

Abstract:

Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

US Patent:

6430082, Aug 6, 2002

Filed:

Aug 30, 2001

Appl. No.:

09/943525

Inventors:

Jeff A. McClain - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1124

US Classification:

365149, 365 51

Abstract:

Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

US Patent:

6493252, Dec 10, 2002

Filed:

Aug 15, 2001

Appl. No.:

09/930522

Inventors:

Jeff A. McClain - Boise ID 83709

International Classification:

G11C 1124

US Classification:

365149, 365 51

Abstract:

Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

US Patent:

6496408, Dec 17, 2002

Filed:

Aug 30, 2001

Appl. No.:

09/943245

Inventors:

Jeff A. McClain - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1124

US Classification:

365149, 365 51

Abstract:

Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

US Patent:

6584010, Jun 24, 2003

Filed:

Aug 30, 2001

Appl. No.:

09/943336

Inventors:

Jeff A. McClain - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1124

US Classification:

365149, 365 51

Abstract:

Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

US Patent:

62923870, Sep 18, 2001

Filed:

Jan 20, 2000

Appl. No.:

9/487975

Inventors:

Jeff A. McClain - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1124

US Classification:

365149

Abstract:

Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

US Patent:

20190130961, May 2, 2019

Filed:

Dec 21, 2018

Appl. No.:

16/231327

Inventors:

- Boise ID, US
Jeff A. McClain - Nampa ID, US
Brian P. Callaway - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 11/406
G11C 7/10

Abstract:

Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may he configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

US Patent:

20190051344, Feb 14, 2019

Filed:

Oct 15, 2018

Appl. No.:

16/160801

Inventors:

- BOISE ID, US
Jeff A. McClain - Nampa ID, US
Brian P. Callaway - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G11C 11/406
G11C 7/10

Abstract:

Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.