Jeff Van Tran

US Patent:

20020060594, May 23, 2002

Filed:

Dec 3, 1999

Appl. No.:

09/454314

Inventors:

DANIEL LAWRENCE STASIAK - ROCHESTER MN, US
JAMES DAVID STROM - ROCHESTER MN, US
JEFF V. TRAN - ROCHESTER MN, US

International Classification:

H03K019/00

US Classification:

327/295000

Abstract:

A method and apparatus are provided for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip. The apparatus for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip includes a first clock circuit generating a first clock signal. A first level inverter is coupled to the first clock circuit receiving the first clock signal. A clock multiplier is coupled to the first level inverter, generating a multiplied clock signal. A plurality of inverters are coupled to the clock multiplier for driving logic circuits within the VLSI circuit chip at the multiplied clock signal.

US Patent:

20130054845, Feb 28, 2013

Filed:

Aug 31, 2011

Appl. No.:

13/222362

Inventors:

Prashanth Nimmala - Beaverton OR, US
Robert J. Greiner - Beaverton OR, US
Lily P. Looi - Portland OR, US
Rupin H. Vakharwala - Hillsboro OR, US
Marcus W. Song - Hillsboro OR, US
James A. Beavens - Portland OR, US
Aimee D. Wood - Hillsboro OR, US
Jeff V. Tran - Hillsboro OR, US

International Classification:

G06F 13/14

US Classification:

710 36

Abstract:

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

US Patent:

60940727, Jul 25, 2000

Filed:

Mar 16, 1999

Appl. No.:

9/268923

Inventors:

Andrew Douglas Davies - Rochester MN
Salvatore N. Storino - Rochester MN
Jeff V. Tran - Rochester MN
Robert Russell Williams - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096
H03K 19094
H03K 1920
H03K 19003

US Classification:

326 98

Abstract:

In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode.

US Patent:

6278157, Aug 21, 2001

Filed:

Jan 29, 1999

Appl. No.:

9/240991

Inventors:

Jeff Van Tran - Rochester MN
Salvatore N. Storino - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2901

US Classification:

257347

Abstract:

The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

US Patent:

61508691, Nov 21, 2000

Filed:

Apr 9, 1999

Appl. No.:

9/289034

Inventors:

Salvatore N. Storino - Rochester MN
Jeff V. Tran - Rochester MN
Robert Russell Williams - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 301

US Classification:

327534

Abstract:

Methods and apparatus are provided for body control in silicon-on-insulator (SOI) domino circuits. The silicon-on-insulator (SOI) domino circuit includes a clock input and an input transistor stack including a plurality of input transistors. Each of the plurality of input transistors receives a data input. An intermediate precharge node is connected to the input transistor stack. An output inverter is connected to the intermediate precharge node. The output inverter includes a pair of silicon-on-insulator (SOI) transistors. A clocked transistor is connected to a body of at least one of the pair of silicon-on-insulator (SOI) transistors. The clocked transistor predischarges the body of the SOI transistor. Another clocked transistor is connected between ground and a body of an evaluate transistor connected to the input transistor stack. The body of the evaluate transistor is predischarged by the clocked transistor.

US Patent:

62716867, Aug 7, 2001

Filed:

Dec 29, 2000

Appl. No.:

9/751270

Inventors:

Jeff Van Tran - Rochester MN
Salvatore N. Storino - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1920
H03K 19094
H03K 19096

US Classification:

326121

Abstract:

The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

US Patent:

6188247, Feb 13, 2001

Filed:

Jan 29, 1999

Appl. No.:

9/239289

Inventors:

Salvatore N. Storino - Rochester MN
Jeff Van Tran - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096

US Classification:

326 98

Abstract:

The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.