Jeffery N Hunt

US Patent:

56213387, Apr 15, 1997

Filed:

Jan 11, 1996

Appl. No.:

8/584105

Inventors:

Lin-Shih Liu - Fremont CA
Syed B. Raza - Sunnyvale CA
Hagop Nazarian - San Jose CA
George M. Ansel - Starkville MS
Stephen M. Douglass - Saratoga CA
Jeffery S. Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 19173
H03K 190948

US Classification:

326 46

Abstract:

A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

US Patent:

55024033, Mar 26, 1996

Filed:

Dec 20, 1994

Appl. No.:

8/360469

Inventors:

Lin-Shih Liu - Fremont CA
Syed B. Raza - Sunnyvale CA
Hagop Nazarian - San Jose CA
George M. Ansel - Starkville MS
Stephen M. Douglass - Saratoga CA
Jeffery S. Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 19173
H03K 190948

US Classification:

326 46

Abstract:

A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.