Jeffrey Dean Andrews

US Patent:

6686915, Feb 3, 2004

Filed:

Apr 19, 2001

Appl. No.:

09/838624

Inventors:

Jeffrey A. Andrews - Sunnyvale CA

Assignee:

Webtv Networks, Inc. - Mountain View CA

International Classification:

G06T 1540

US Classification:

345422, 345426

Abstract:

Systems and methods for accurately and realistically rendering a visual effect such as fog, colored liquids, gels, smoke, mists, and the like for which the visual appearance of the effect can change with respect to depth and for which the effect is rendered on a output display so as to be generally contained. Depth values are identified and passed to a visibility function in order to yield corresponding visibility values. An adjusted visibility function blends the obtained visibility values and yields an adjusted visibility value. This process for obtaining an adjusted visibility value is performed for every pixel of a display screen that is used to render the visual effect in order to accurately render the visual effect as it would be perceived in the real world.

US Patent:

6862027, Mar 1, 2005

Filed:

Jun 30, 2003

Appl. No.:

10/611415

Inventors:

Jeffrey A. Andrews - Sunnyvale CA, US
Nicholas R. Baker - Cupertino CA, US
J. Andrew Goossen - Issaquah WA, US
Michael Abrash - Kirkland WA, US

Assignee:

Microsoft Corp. - Redmond WA

International Classification:

G06F015/80

US Classification:

345505, 345557, 345419, 711122, 382233

Abstract:

A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.

US Patent:

7030887, Apr 18, 2006

Filed:

Nov 12, 2003

Appl. No.:

10/706690

Inventors:

Jeffrey A. Andrews - Sunnyvale CA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G09G 5/339
G09G 5/02
G06T 17/20
G06T 15/50

US Classification:

345592, 345422, 345426, 345539, 345561

Abstract:

Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

US Patent:

7116337, Oct 3, 2006

Filed:

Feb 1, 2006

Appl. No.:

11/275878

Inventors:

Jeffrey A. Andrews - Sunnyvale CA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G09G 5/02
G06T 15/20
G06T 17/20
G09G 5/339

US Classification:

345592, 345422, 345426, 345539, 345561

Abstract:

Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and, for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

US Patent:

7333114, Feb 19, 2008

Filed:

Dec 30, 2004

Appl. No.:

11/027454

Inventors:

Jeffrey A. Andrews - Sunnyvale CA, US
Nicholas R. Baker - Cupertino CA, US
J. Andrew Goossen - Issaquah WA, US
Michael Abrash - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 15/16
G06F 12/00
G09G 5/36

US Classification:

345503, 345557, 711118

Abstract:

A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.

US Patent:

7355601, Apr 8, 2008

Filed:

Dec 16, 2005

Appl. No.:

11/303525

Inventors:

Jeffrey A. Andrews - Sunnyvale CA, US
Nicholas R. Baker - Cupertino CA, US
J. Andrew Goossen - Issaquah WA, US
Russell D. Hoover - Rochester MN, US
Eric O. Mejdrich - Rochester MN, US
Sandra S. Woodward - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY
Microsoft Corporation - Redmond WA

International Classification:

G06F 12/08
G06F 9/46
G06F 13/20
G06F 15/80
G06F 13/28
G09G 9/36
G06T 15/00
G06F 15/16
G06F 15/78

US Classification:

345505, 345502, 345557, 345543, 345574, 711 3, 711118, 711125, 711143, 712 10, 712 34, 382233

Abstract:

A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

US Patent:

7650539, Jan 19, 2010

Filed:

Jun 30, 2005

Appl. No.:

11/170818

Inventors:

Susan E. Carrie - Mountain View CA, US
Jeffrey A. Andrews - Sunnyvale CA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 11/00

US Classification:

714 47

Abstract:

A debugging architecture includes a set of debug counters for counting one or more events based on a set of signals from a device being monitored. The architecture provides for observing the outputs of the debug counters during operation of the device. The outputs of the counters are provided to an output bus (e. g. , a Debug Bus) via an output bus interface during operation of the device being monitored. A data gathering system can access the output bus in order to gather the data from the counters for analysis.

US Patent:

7925903, Apr 12, 2011

Filed:

Jun 28, 2007

Appl. No.:

11/770041

Inventors:

Ankur Varma - San Francisco CA, US
Jeffrey Allen Andrews - Sunnyvale CA, US
Susan Elizabeth Carrie - Mountain View CA, US
Rune Hartung Jensen - Cupertino CA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 1/32

US Classification:

713300

Abstract:

Power is dynamically conserved in a device by analyzing past processing performance of the device and predicting the amount of power required for future execution. In an example embodiment, a video frame is analyzed to determine what portion of the video frame was needed to render data. If less than the full video frame was needed, at least one power conservation technique is applied to the device for subsequent rendering of data. Power conservation techniques include adjusting the operating frequency of circuitry utilized to render data, adjusting the voltage applied to circuitry utilized to render data, and/or turning off/on circuitry utilized to render data.