Jeffrey J Borenstein

US Patent:

6521041, Feb 18, 2003

Filed:

Apr 9, 1999

Appl. No.:

09/289514

Inventors:

Kenneth C. Wu - Boston MA
Eugene A. Fitzgerald - Windham NH
Jeffrey T. Borenstein - Belmont MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

C30B 2502

US Classification:

117 94, 117 95, 117 97, 117915, 117939, 148 331

Abstract:

A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si Ge alloy with x generally between 0. 2 and 0. 5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i. e. , âmicromachinedâ, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7Ã10 cm of boron or undoped Si Ge alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i. e.

US Patent:

6673694, Jan 6, 2004

Filed:

Jan 2, 2002

Appl. No.:

10/038890

Inventors:

Jeffrey T. Borenstein - Holliston MA

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

H01L 2176

US Classification:

438411, 438 50, 438 53, 438696, 438700, 438701, 438456, 257414, 257415, 257416, 257417

Abstract:

The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.

US Patent:

6862934, Mar 8, 2005

Filed:

Oct 4, 2002

Appl. No.:

10/264887

Inventors:

Marc S. Weinberg - Needham MA, US
Anthony S. Kourepenis - Acton MA, US
William D. Sawyer - Lexington MA, US
Jeffrey T. Borenstein - Holliston MA, US
James H. Connelly - Weymouth MA, US
Amy E. Duwel - Cambridge MA, US
Christopher M. Lento - Boston MA, US
James R. Cousens - Hanson MA, US

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

G01P015/08

US Classification:

7350412, 7350402, 7350416

Abstract:

A tuning fork gyroscope typically including at least one proof mass with an upper sense plate disposed above the proof mass and a lower sense plate disposed below the proof mass and means for sensing changes in the nominal gaps between the sense plate and the proof mass and for outputting a signal indicative of the gyroscope angular rate.

US Patent:

6946314, Sep 20, 2005

Filed:

Aug 15, 2003

Appl. No.:

10/642315

Inventors:

William D. Sawyer - Arlington MA, US
Jeffrey T. Borenstein - Holliston MA, US

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

H01L021/76

US Classification:

438 50, 438456

Abstract:

The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

US Patent:

7172919, Feb 6, 2007

Filed:

Oct 20, 2004

Appl. No.:

10/970067

Inventors:

Marc S. Weinberg - Needham MA, US
Anthony S. Kourepenis - Acton MA, US
William D. Sawyer - Lexington MA, US
Jeffrey T. Borenstein - Holliston MA, US
James H. Connelly - Weymouth MA, US
Amy E. Duwel - Cambridge MA, US
Christopher M. Lento - Boston MA, US
James R. Cousens - Hanson MA, US

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

H01L 21/00

US Classification:

438 50, 438 51

Abstract:

A method for reducing errors in a tuning fork gyroscope includes determining a first distance, g, between an upper sense plate and a proof mass and a second distance, g, between a lower sense plate and the proof mass. The method further includes applying a first voltage, V, to the upper sense plate and a second voltage, V, to the lower sense plate, wherein the ratio of the first voltage and the second voltage is a function of the first distance and the second distance.

US Patent:

7335527, Feb 26, 2008

Filed:

Sep 20, 2005

Appl. No.:

11/231103

Inventors:

William D. Sawyer - Arlington MA, US
Jeffrey T. Borenstein - Holliston MA, US

International Classification:

H01L 21/00
B81C 1/00

US Classification:

438 50, 438458

Abstract:

The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

US Patent:

7371400, May 13, 2008

Filed:

Jan 2, 2002

Appl. No.:

10/038891

Inventors:

Jeffrey T. Borenstein - Cambridge MA, US
Kevin R. King - Cambridge MA, US
Hidetomi Terai - Osaka, JP
Joseph P. Vacanti - Boston MA, US

Assignee:

The General Hospital Corporation - Boston MA

International Classification:

A61F 2/00
C12N 11/02
C12N 11/08
C12N 5/06
C12N 5/08

US Classification:

424423, 435177, 435180, 435395

Abstract:

The invention provides for translating two-dimensional microfabrication technology into the third dimension. Two-dimensional templates are fabricated using high-resolution molding processes. These templates are then bonded to form three-dimensional scaffold structures with closed lumens. The scaffolds can serve as the template for cell adhesion and growth by cells that are added to the scaffolds through the vessels, holes or pores. These scaffolds can be formed by layering techniques, to interconnect flat template sheets to build up a fully vascularized organ.

US Patent:

7402425, Jul 22, 2008

Filed:

Mar 2, 2004

Appl. No.:

10/791108

Inventors:

Marc S. Weinberg - Needham MA, US
Jeffrey Borenstein - Holliston MA, US
Christopher E. Dubé - Lexington MA, US
Ralph Hopkins - Chestnut Hill MA, US
Edwin Carlen - Cambridge MA, US

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

C12M 1/34

US Classification:

4352872, 435 71, 4352831, 7386147, 73262, 73263, 73269, 73279, 436149, 436806, 204282, 422 50, 422 8201, 422 8202, 422 61, 422 681

Abstract:

Electrostatic capacitance measurements are used to detect chemical or biological analytes, or chemical interactions, with great sensitivity. A diaphragm is coated with a material capable of selectively interacting with an analyte of interest, and interaction of the analyte with the coating exerts stresses tangential to the diaphragm's surface. These stresses cause diaphragm displacements that are sensed as varying capacitance.