Jeffrey Allen Gilbert

US Patent:

7124229, Oct 17, 2006

Filed:

Nov 2, 2004

Appl. No.:

10/980737

Inventors:

Jeffrey D. Gilbert - Portland OR, US
Harris D. Joyce - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710309, 710113

Abstract:

A method and apparatus for improved performance for handling priority agent bus requests when symmetric agent bus parking is enabled is disclosed. In one embodiment, a modified priority agent may be used. The modified priority agent may assert an unused symmetric agent bus request when it asserts its priority agent bus request. When a symmetric agent parks on the bus, continually asserting its symmetric agent bus request, the assertion of the otherwise unused symmetric agent bus request may cause the symmetric agent to withdraw its symmetric agent bus request. This may reduce bus response time for subsequent modified priority agent bus requests.

US Patent:

7228387, Jun 5, 2007

Filed:

Jun 30, 2003

Appl. No.:

10/611619

Inventors:

William G. Auld - Portland OR, US
Jeffrey D. Gilbert - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711137, 711167, 711213

Abstract:

A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.

US Patent:

7484044, Jan 27, 2009

Filed:

Sep 12, 2003

Appl. No.:

10/662093

Inventors:

Jeffrey D. Gilbert - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711144, 711122, 711145, 711146, 711136, 711141, 711142, 711143

Abstract:

A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache coherency state. The joint cache coherency state may have a first state for the inner interface and a second state for the outer interface, where the second state has higher privilege than the first state. In one embodiment this may promote speculative invalidation. In other embodiments this may reduce snoop transactions on the inner interface.

US Patent:

7555597, Jun 30, 2009

Filed:

Sep 8, 2006

Appl. No.:

11/518480

Inventors:

Durgesh Srivastava - Santa Clara CA, US
Jeffrey D. Gilbert - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711113, 711130, 711145, 711146, 711147, 711154, 370389

Abstract:

Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.

US Patent:

7581068, Aug 25, 2009

Filed:

Jun 29, 2006

Appl. No.:

11/479327

Inventors:

Jeffrey D. Gilbert - Portland OR, US
Kai Cheng - Portland OR, US
Liqun Cheng - Salt Lake City UT, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

711146, 711141

Abstract:

A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a processor. A coherency engine updates the entries in the snoop filter such that an entry is removed from the snoop filter if the entry exits the exclusive state. To ensure data coherency, the coherency engine implements a sequencing rule that decouples a read request from a write request.

US Patent:

7647476, Jan 12, 2010

Filed:

Mar 14, 2006

Appl. No.:

11/374708

Inventors:

Christopher Mozak - Beaverton OR, US
Jeffrey D. Gilbert - Portland OR, US
Ganapati Srinivasa - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38
G06F 13/14
G11C 7/10

US Classification:

712200, 710305, 36518902, 36518918

Abstract:

In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

US Patent:

7689778, Mar 30, 2010

Filed:

Nov 30, 2004

Appl. No.:

11/000768

Inventors:

Yen-Cheng Liu - Portland OR, US
Krishnakanth V. Sistla - Hillsboro OR, US
George Cai - Lake Oswego OR, US
Jeffrey D. Gilbert - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

711146, 711121, 711130

Abstract:

In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

US Patent:

7779188, Aug 17, 2010

Filed:

Mar 22, 2005

Appl. No.:

11/087914

Inventors:

Bryan L. Spry - Portland OR, US
Harris D. Joyce - Portland OR, US
Balaji P. Ramamoorthy - Beaverton OR, US
Jeffrey D. Gilbert - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710112, 710310

Abstract:

A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.