Jeffrey D Gilbert

US Patent:

6339022, Jan 15, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/475712

Inventors:

Arne W. Ballantine - Coldspring NY
Cheryl G. Faltermeier - Lagrange NY
Jeffrey D. Gilbert - Burlington VT
Ronald D. Goldblatt - Yorktown Heights NY
Nancy A. Greco - Lagrangeville NY
Stephen E. Greco - Lagrangeville NY
Frank V. Liucci - Wappingers Falls NY
Glenn Robert Miller - Essex Junction VT
Bruce A. Root - Westford VT
Andrew H. Simon - Fishkill NY
Anthony K. Stamper - Williston VT
Ronald A. Warren - Essex Junction VT
David H. Yao - Essex VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438660, 438663, 438687

Abstract:

A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

US Patent:

6417070, Jul 9, 2002

Filed:

Dec 13, 2000

Appl. No.:

09/735988

Inventors:

Arne W. Ballantine - Cold Spring NY
Jeffrey S. Brown - Middlesex VT
Jeffrey D. Gilbert - South Burlington VT
James J. Quinlivan - Essex Junction VT
James A. Slinkman - Montpelier VT
Anthony C. Speranza - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

438424, 438435, 438437, 438770

Abstract:

A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.

US Patent:

6552411, Apr 22, 2003

Filed:

Mar 16, 2001

Appl. No.:

09/809887

Inventors:

Arne W. Ballantine - Round Lake NY
John J. Ellis-Monaghan - Grande Isle VT
Jeffrey D. Gilbert - South Burlington VT
Glenn R. Miller - Essex Junction VT
James A. Slinkman - Montpelier VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

257530, 257422, 438510, 438659, 438660, 438514, 438572, 118500, 204164

Abstract:

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

US Patent:

6580140, Jun 17, 2003

Filed:

Sep 18, 2000

Appl. No.:

09/665584

Inventors:

Arne W. Ballantine - Cold Spring NY
Jeffrey D. Gilbert - South Burlington VT
Robert G. Miller - Essex Junction VT
Amy L. Myrick - Waterbury Ctr. CT
Ronald A. Warren - Milton VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31058

US Classification:

257467, 257 43, 257 48, 257751

Abstract:

A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600Â C. , wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600Â C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafers surface. In addition, the monitor may be reconditioned for repeated use by heating the monitor in a hydrogen ambient environment to convert the oxide layer to unoxidized copper.

US Patent:

6660664, Dec 9, 2003

Filed:

Mar 31, 2000

Appl. No.:

09/541091

Inventors:

James W. Adkisson - Jericho VT
Arne W. Ballantine - Cold Spring NY
Matthew D. Gallagher - Burlington VT
Peter J. Geiss - Underhill VT
Jeffrey D. Gilbert - Burlington VT
Shwu-Jen Jeng - Wappingers Falls NY
Donna K. Johnson - Underhill VT
Robb A. Johnson - South Burlington VT
Glen L. Miles - Essex Junction VT
Kirk D. Peterson - Essex Junction VT
James J. Toomey - Poughkeepsie NY
Tina Wagner - Newburgh NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H01L 2131

US Classification:

438791, 438792, 438257, 438260

Abstract:

A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

US Patent:

6670263, Dec 30, 2003

Filed:

Mar 10, 2001

Appl. No.:

09/802702

Inventors:

Arne W. Ballantine - Round Lake NY
Kevin K. Chan - Staten Island NY
Jeffrey D. Gilbert - Burlington VT
Kevin M. Houlihan - Boston MA
Glen L. Miles - Essex Junction VT
James J. Quinlivan - Essex Junction VT
Samuel C. Ramac - Poughkeepsie NY
Michael B. Rice - Colchester VT
Beth A. Ward - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 213205

US Classification:

438592, 438585, 438199, 438287, 438655

Abstract:

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

US Patent:

6703283, Mar 9, 2004

Filed:

Feb 4, 1999

Appl. No.:

09/244958

Inventors:

Arne W. Ballantine - South Burlington VT
Douglas D. Coolbaugh - Essex Junction VT
Jeffrey Gilbert - Winooski VT
Joseph R. Greco - South Burlington VT
Glenn R. Miller - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21331

US Classification:

438309, 438313, 438318, 438 48, 438312, 438205, 438235, 257197, 257351, 257361, 257370, 257373, 257474, 257477, 257526, 257541, 257552, 257565

Abstract:

A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

US Patent:

6759260, Jul 6, 2004

Filed:

Apr 23, 2003

Appl. No.:

10/421986

Inventors:

Arne W. Ballantine - Cold Spring NY
Jeffrey D. Gilbert - South Burlington VT
Robert G. Miller - Essex Junction VT
Amy L. Myrick - Waterbury Ctr. VT
Ronald A. Warren - Milton VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2166

US Classification:

438 18, 438 54, 438104, 438653

Abstract:

A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600Â C. , wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600Â C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafers surface. In addition, the monitor may be reconditioned for repeated use by heating the monitor in a hydrogen ambient environment to convert the oxide layer to unoxidized copper.