Jeffrey D Hall

US Patent:

7024637, Apr 4, 2006

Filed:

Sep 29, 2003

Appl. No.:

10/673721

Inventors:

Jeffrey A. Hall - San Jose CA, US
Aritharan Thurairajaratnam - San Jose CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 9, 716 12, 716 14

Abstract:

A method of designing a packaged circuit, including a substrate and a circuit. The circuit is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known function and a known contact pattern. The circuit is designed by selecting desired functional blocks according to functions desired for the circuit. The substrate is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known contact pattern, a known signal trace routing layer pattern, a known ground plane layer pattern, and a known power plane layer pattern. A given one of the substrate functional blocks is associated with a given one of the circuit functional blocks. The substrate is designed by selecting substrate functional blocks associated with the desired ones of the circuit functional blocks.

US Patent:

7180011, Feb 20, 2007

Filed:

Mar 17, 2006

Appl. No.:

11/276938

Inventors:

Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01R 13/46
H01R 12/04
H05K 5/00

US Classification:

174520, 174261, 174255, 257776, 257774

Abstract:

A method of routing an integrated circuit package design includes steps of receiving as input at least a portion of an integrated circuit design including a differential pair of two electrical conductors, calculating a value of length mismatch between the two electrical conductors, calculating an added trace length to compensate for an impedance discontinuity of a shorter one of the two electrical conductors, and extending the shorter one of the two electrical conductors by routing the added trace length entirely inside an area surrounded by a contact pad that electrically terminates the shorter one of the two electrical conductors. The routing for the differential pair with the added trace length is generated as output in the integrated circuit design.

US Patent:

7298036, Nov 20, 2007

Filed:

Nov 18, 2005

Appl. No.:

11/283340

Inventors:

Leah M. Miller - Fremont CA, US
Jeffrey A. Hall - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 23/02

US Classification:

257686, 257777, 257E23069, 257E2307

Abstract:

A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having a die side and a circuit board side. The package substrate has a size that is consistent for all of the package substrates in the family of package substrates. The die side has integrated circuit contacts disposed in a pattern designed to make electrical connections to a given integrated circuit in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit. The circuit board side has circuit board contacts disposed in a pattern and with functional assignments that are consistent for all of the package substrates in the family of package substrates.

US Patent:

7405946, Jul 29, 2008

Filed:

May 5, 2005

Appl. No.:

11/122370

Inventors:

Jeffrey A. Hall - San Jose CA, US
Farshad Ghahghahi - Los Gatos CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 7/00

US Classification:

361783, 361782, 361792, 174261

Abstract:

A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in first ordered channels of adjacent receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern. The first ordered channels are ordered to match an order of transmitter channels of a connector or another component on a printed circuit board to which the transmitter differential pairs are routed, and the second ordered channels are ordered to match an order of receiver channels of a connector or another component on a printed circuit board to which the receiver differential pairs are routed.

US Patent:

8049340, Nov 1, 2011

Filed:

Mar 22, 2006

Appl. No.:

11/277188

Inventors:

Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 23/48

US Classification:

257777, 257E23019, 257E23151, 257758

Abstract:

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

US Patent:

8288269, Oct 16, 2012

Filed:

Oct 4, 2011

Appl. No.:

13/252632

Inventors:

Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438622, 257758, 257E21536

Abstract:

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

US Patent:

8324019, Dec 4, 2012

Filed:

May 21, 2009

Appl. No.:

12/469985

Inventors:

George C. Tang - Cupertino CA, US
Lizhi Zhong - Sunnyvale CA, US
Freeman Y. Zhong - San Ramon CA, US
Wenyi Jin - Santa Clara CA, US
Jeffrey A. Hall - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/00

US Classification:

438106, 438107, 438108

Abstract:

A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

US Patent:

20060043603, Mar 2, 2006

Filed:

Aug 31, 2004

Appl. No.:

10/932174

Inventors:

Yogendra Ranade - Fremont CA, US
Rajagopalan Parthasarathy - Milpitas CA, US
Jeffrey Hall - San Jose CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21/44
H01L 23/48

US Classification:

257778000, 438108000, 257779000, 438612000, 257782000

Abstract:

Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is lower than that of the solder ball. Reflow is then performed at a relative low temperature that is high enough for reflowing the bonding agent, yet at the same time, lower than what would be necessary to reflow the solder material. Since, the electrical system is not subjected to the high temperatures necessary for reflowing the solder material, the electronic system experiences less high-temperature related damage.