Jeffrey L Krieger

US Patent:

6501664, Dec 31, 2002

Filed:

Jun 30, 2000

Appl. No.:

09/608183

Inventors:

Jeffrey L. Krieger - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 706

US Classification:

361782, 361777, 361780, 257724, 29840

Abstract:

A wiring lay-out is provided, for electrically connecting a decoupling cap on a front surface of a multilayer printed circuit board (e. g. , a motherboard), with a surface-mounted electrical component (e. g. , a micro-ball grid array packaged semiconductor device, such as a PC core logic chip set) on the front surface of the printed circuit board. The wiring lay-out includes a wiring portion formed from a copper plane on the front surface of the printed circuit board; this wiring portion, providing electrical connection from one of the balls of the ball grid array to the decoupling cap, is provided only on the front surface of the printed circuit board. In order to provide a route for the wiring between the electrical component and decoupling cap, vias through the printed circuit board are positioned in a row with bonding pads. All decoupling caps on the printed circuit board are provided on the front surface of the printed circuit board.

US Patent:

6900992, May 31, 2005

Filed:

Sep 18, 2001

Appl. No.:

09/955230

Inventors:

Christopher J. Kelly - Portland OR, US
Jeffrey L. Krieger - Portland OR, US
Raymond P. Askew - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K007/02
H05K007/06
H05K007/08
H05K007/10

US Classification:

361794, 361780

Abstract:

A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

US Patent:

7356796, Apr 8, 2008

Filed:

Jun 28, 2005

Appl. No.:

11/170558

Inventors:

Cliff Lee - Portland OR, US
Scott T. Gardiner - Beaverton OR, US
Jeffrey L. Krieger - Portland OR, US
Jen-Tai Hsu - El Dorado Hills CA, US
Fei Deng - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 8

Abstract:

A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers are adjacent. Other structures and methods are also described and claimed.

US Patent:

20060294279, Dec 28, 2006

Filed:

Jun 28, 2005

Appl. No.:

11/168607

Inventors:

Kenneth McKee - Folsom CA, US
Jeffrey Krieger - Portland OR, US

International Classification:

H05K 7/10

US Classification:

710301000

Abstract:

In one embodiment, an apparatus to enable Peripheral Component Interconnect Express (PCIe) connector multiplexing is presented. The apparatus comprises a continuity module to insert into a first PCIe connector slot and to route a first set of data lanes coupled to the first PCIe connector slot to a second set of data lanes coupled to both of the first PCIe connector slot and a second PCIe connector slot. Other embodiments are also described.

US Patent:

20210153351, May 20, 2021

Filed:

Dec 18, 2020

Appl. No.:

17/127829

Inventors:

- Santa Clara CA, US
George VERGIS - Portland OR, US
Jeffrey KRIEGER - Portland OR, US

International Classification:

H05K 1/11
H01R 12/52
H05K 5/02
H05K 1/18
G11C 5/06

Abstract:

Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

US Patent:

20160344379, Nov 24, 2016

Filed:

Oct 30, 2015

Appl. No.:

14/929154

Inventors:

- Santa Clara CA, US
Vaughn GROSSNICKLE - Beaverton OR, US
Nasser KURD - Portland OR, US
Jeffrey KRIEGER - Portland OR, US

International Classification:

H03K 5/156
H03K 3/03

Abstract:

Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

US Patent:

20150001933, Jan 1, 2015

Filed:

Jun 28, 2013

Appl. No.:

13/931314

Inventors:

Alexander B. UAN-ZO-LI - Hillsboro OR, US
Jorege P. RODRIGUEZ - Portland OR, US
Sofia C. HAO - Beaverton OR, US
David W. BROWNING - Beaverton OR, US
Jeffrey A. CARLSON - Portland OR, US
Tawfik M. RAHAL-ARABI - Tigard OR, US
Jeffrey L. KRIEGER - Portland OR, US

International Classification:

H02M 3/158

US Classification:

307 31

Abstract:

An electronic device may include a plurality of voltage rails to provide voltages to components of a load, a plurality of voltage regulators, and a buck converter apparatus to separately couple to more than one of the plurality of voltage rails and to provide a voltage to at least a specific one of the voltage rails.

US Patent:

20140218088, Aug 7, 2014

Filed:

Dec 15, 2011

Appl. No.:

13/993137

Inventors:

- Santa Clara CA, US
Vaughn Grossnickle - Beaverton OR, US
Nasser Kurd - Portland OR, US
Jeffrey Krieger - Portland OR, US

International Classification:

H03K 5/04

US Classification:

327175

Abstract:

Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.