Jeffrey Floyd Mitchell

Address:

3900 Texas Wildlife Trl, Austin, TX 78735

VIN:

5FNRL38807B038088

Make:

HONDA

Model:

ODYSSEY

Year:

2007

US Patent:

6687780, Feb 3, 2004

Filed:

Nov 2, 2000

Appl. No.:

09/706238

Inventors:

Bruno W. Garlepp - Austin TX
Richard M. Barth - Ashland OR
Kevin S. Donnelly - Los Altos CA
Ely K. Tsern - Los Altos CA
Craig E. Hampel - San Jose CA
Jeffrey D. Mitchell - Santa Clara CA
James A. Gasbarro - Fox Chapel PA
Fredrick A. Ware - Los Altos Hills CA
Donald V. Perino - North Potomac MD

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 1340

US Classification:

710305, 326 30

Abstract:

A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.

US Patent:

7222209, May 22, 2007

Filed:

Dec 16, 2003

Appl. No.:

10/738293

Inventors:

Bruno W. Garlepp - Austin TX, US
Richard M. Barth - Ashland OR, US
Kevin S. Donnelly - Los Altos CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Jeffrey D. Mitchell - Santa Clara CA, US
James A. Gasbarro - Fox Chapel PA, US
Fredrick A. Ware - Los Altos Hills CA, US
Donald V. Perino - North Potomac MD, US

Assignee:

Rambus, Inc. - Los Altos CA

International Classification:

G06F 13/14

US Classification:

710305, 710306, 326 30

Abstract:

A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

US Patent:

7536494, May 19, 2009

Filed:

May 22, 2007

Appl. No.:

11/752242

Inventors:

Bruno W. Garlepp - Austin TX, US
Richard M. Barth - Ashland OR, US
Kevin S. Donnelly - Los Altos CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Jeffrey D. Mitchell - Santa Clara CA, US
James A. Gasbarro - Fox Chapel PA, US
Fredrick A. Ware - Los Altos Hills CA, US
Donald V. Perino - North Potomac MD, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 13/36

US Classification:

710306, 710305, 710310, 711100

Abstract:

A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.