Jeffrey C Morrow

US Patent:

20190089126, Mar 21, 2019

Filed:

Sep 20, 2017

Appl. No.:

15/710101

Inventors:

- Durham NC, US
Michael J. Bruno - Holly Springs NC, US
Jeffrey Alan Morrow - Redmond WA, US
Abhishek Yadav - Cary NC, US

International Classification:

H01S 5/024
H01S 5/022
H01L 35/32
H01L 35/34
H01L 35/08

Abstract:

Embodiments of a Transistor Outline (TO) can package having an integrated Thermoelectric Cooler (TEC) and methods of manufacturing a TO can package having an integrated TEC are disclosed. In some embodiments, a TO can package comprises a TO header and a TEC on a surface of the TO header. The TEC comprises an insulation layer on a surface of the TO header, where the insulation layer has a thickness that is less than 100 micrometers and comprises one or more thermally and electrically conductive materials. The TEC further comprises a plurality of thermoelectric devices on a surface of the insulation layer opposite the TO header. The thin insulation layer, as opposed to a relatively thick bottom header of a stand-alone TEC, enables taller N-type and P-type legs for the thermoelectric devices, and thus a higher Coefficient of Performance (COP), within a given height for the TEC.