Jeffrey S Niew

US Patent:

20120161259, Jun 28, 2012

Filed:

Oct 21, 2011

Appl. No.:

13/278351

Inventors:

Peter V. Loeppert - Hoffman Estates IL, US
Daniel Giesecke - West Chicago IL, US
Anthony Minervini - Palos Hills IL, US
Jeffrey Niew - Burr Ridge IL, US
Lawrence Grunert - Lombard IL, US

International Classification:

H01L 29/84

US Classification:

257416, 257E29324

Abstract:

A package is provided. The package has a substrate and a cover. A MEMS die is provided having a diaphragm. A CMOS die is provided wherein at least a portion of the CMOS die is positioned between the diaphragm and the substrate.

US Patent:

6351011, Feb 26, 2002

Filed:

Jan 12, 2000

Appl. No.:

09/481927

Inventors:

Stephen J. Whitney - Lake Zurich IL
Jeffrey S. Niew - Burr Ridge IL
Michael J. Weber - Wheeling IL

Assignee:

Littlefuse, Inc. - Desplaines IL

International Classification:

H01L 2362

US Classification:

257355, 257787, 257659

Abstract:

A number of integrated circuit dies having on board protection against electrical overstress (EOS) transients are provided. Generally, the devices have an integrated circuit die with an outer periphery and a functional die area. A plurality of conductive input/output pads are formed on the integrated circuit die. Typically, a first conductive guard rail is disposed on the integrated circuit die and forms a gap between each one of the input/output pads. A voltage variable material is disposed in the gaps between the conductive guard rail and the input/output pads. Typically, a plurality of electrical leads are electrically connected to a respective one of the plurality of conductive input/output pads. At normal operating voltages, the voltage variable material is non-conductive. However, in response to an EOS transient, the voltage variable material switches to a low resistance state, providing a conductive path between the conductive guard rail and the input/output pads.