Jeffrey W Patton

US Patent:

6969678, Nov 29, 2005

Filed:

Nov 3, 2003

Appl. No.:

10/700711

Inventors:

Robert J. Chiu - Santa Clara CA, US
Paul R. Besser - Sunnyvale CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Jeffrey P. Patton - Santa Clara CA, US
Austin C. Frenkel - San Jose CA, US
Thorsten Kammler - Ottendorft-Okrilla, DE
Errol Todd Ryan - Wappingers Fall NY, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/44

US Classification:

438655, 438654, 438683

Abstract:

A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

US Patent:

7005376, Feb 28, 2006

Filed:

Jul 7, 2003

Appl. No.:

10/615086

Inventors:

Robert J. Chiu - Santa Clara CA, US
Jeffrey P. Patton - Santa Clara CA, US
Paul R. Besser - Sunnyvale CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/00

US Classification:

438664, 438592, 438586

Abstract:

A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

US Patent:

7049666, May 23, 2006

Filed:

Jun 1, 2004

Appl. No.:

10/859286

Inventors:

Robert J. Chiu - San Jose CA, US
Jeffrey P. Patton - Santa Clara CA, US
Paul R. Besser - Sunnyvale CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29/94
H01L 21/44

US Classification:

257384, 257382

Abstract:

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

US Patent:

7064067, Jun 20, 2006

Filed:

Feb 2, 2004

Appl. No.:

10/770905

Inventors:

Paul L. King - Mountain View CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Jeffrey P. Patton - Santa Clara CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/336
H01L 21/44

US Classification:

438682, 438299, 438663, 438664

Abstract:

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

US Patent:

7132352, Nov 7, 2006

Filed:

Aug 6, 2004

Appl. No.:

10/913184

Inventors:

Simon Siu-Sing Chan - Saratoga CA, US
Paul R. Besser - Sunnyvale CA, US
Jeffrey P. Patton - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/28

US Classification:

438581, 438630, 257E23157, 257 21006

Abstract:

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

US Patent:

7151020, Dec 19, 2006

Filed:

May 4, 2004

Appl. No.:

10/839437

Inventors:

Jeffrey P. Patton - Santa Clara CA, US
Austin C. Frenkel - San Jose CA, US
Thorsten Kammler - Ottendorft-Okrilla, DE
Robert J. Chiu - San Jose CA, US
Errol Todd Ryan - Wappingers Falls NY, US
Darin A. Chan - San Francisco CA, US
Paul R. Besser - Sunnyvale CA, US
Paul L. King - Mountain View CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/336
H01L 21/44

US Classification:

438197, 438301, 438655, 438664

Abstract:

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

US Patent:

7307322, Dec 11, 2007

Filed:

Oct 17, 2005

Appl. No.:

11/252493

Inventors:

Robert J. Chiu - Santa Clara CA, US
Jeffrey P. Patton - Santa Clara CA, US
Paul R. Besser - Sunnyvale CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Adavnced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29/76

US Classification:

257384, 257383, 438664, 438586, 438592

Abstract:

A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

US Patent:

7843015, Nov 30, 2010

Filed:

Sep 15, 2005

Appl. No.:

11/229188

Inventors:

Robert J. Chiu - Santa Clara CA, US
Paul R. Besser - Sunnyvale CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Jeffrey P. Patton - Santa Clara CA, US
Austin C. Frenkel - San Jose CA, US
Thorsten Kammler - Ottendorft-Okrilla, DE
Errol Todd Ryan - Wappingers Fall NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 21/02

US Classification:

257384, 257335, 438664, 438655

Abstract:

An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.