Medical School Eastern Virginia Medical School Medical College Graduated: 1988
Procedures:
Chemotherapy
Conditions:
Gastric Cancer Hodgkin's Lymphoma Lung Cancer Malignant Neoplasm of Colon Malignant Neoplasm of Female Breast
Languages:
Chinese English Spanish
Description:
Dr. Patton graduated from the Eastern Virginia Medical School Medical College in 1988. He works in Nashville, TN and 1 other location and specializes in Hematology/Oncology. Dr. Patton is affiliated with Northcrest Medical Center, Saint Thomas Midtown Hospital, Tristar Centennial Medical Center, Tristar Skyline Medical Center and Tristar Southern Hills Medical Center.
Name / Title
Company / Classification
Phones & Addresses
Jeffrey Patton
PATTON FARMS, LTD
Jeffrey Patton
FOUR KINGS REAL ESTATE HOLDINGS LLC
Jeffrey Patton
WORLD WIDE WEB SOLUTIONS LTD
Jeffrey Patton
PATTON/SEGINOT, LLC
Jeffrey Patton
JEFFREY PATTON FOUNDATION
Jeffrey Patton
THE SARTOR/PATTON LLC
Jeffrey Patton
P&L CONSTRUCTION AND DEVELOPMENT, INC
Us Patents
Trenches To Reduce Lateral Silicide Growth In Integrated Circuit Technology
Darin A. Chan - San Francisco CA, US Simon Siu-Sing Chan - Saratoga CA, US Jeffrey P. Patton - Santa Clara CA, US Jacques J. Bertrand - Capitola CA, US
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
Reduction Of Lateral Silicide Growth In Integrated Circuit Technology
Paul L. King - Mountain View CA, US Simon Siu-Sing Chan - Saratoga CA, US Jeffrey P. Patton - Santa Clara CA, US Minh Van Ngo - Fremont CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21/336 H01L 21/44
US Classification:
438682, 438299, 438663, 438664
Abstract:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.