Jeffrey D Potter

US Patent:

7050063, May 23, 2006

Filed:

Feb 11, 2000

Appl. No.:

09/502994

Inventors:

Michael Mantor - Orlando FL, US
John Austin Carey - Winter Springs FL, US
Ralph Clayton Taylor - Deland FL, US
Thomas A. Piazza - Granite Bay CA, US
Jeffrey D. Potter - Winter Springs FL, US
Angel E. Socarras - Lake Mary FL, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345582, 345552, 345557, 345558, 345535, 345564, 345565

Abstract:

A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized.

US Patent:

20060164429, Jul 27, 2006

Filed:

Jan 30, 2006

Appl. No.:

11/344030

Inventors:

Michael Mantor - Orlando FL, US
John Carey - Winter Springs FL, US
Ralph Taylor - Deland FL, US
Thomas Piazza - Granite Bay CA, US
Jeffrey Potter - Winter Springs FL, US
Angel Socarras - Lake Mary FL, US

International Classification:

G09G 5/00

US Classification:

345582000

Abstract:

A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.